ACADEMIA

The widespread use of Supercomputer Graphics and Vision applications has led to a plethora of hardware implementations that are usually expressed using linear algebraic methods. There are two drawbacks with this approach that are posing fundamental challenges to engineers developing hardware and software applications in this area. A Research team at the Computer Science at the University of Southampton, UK has been working on these challenges. The first is the complexity and size of the hardware blocks required to practically realise such applications – particularly floating point multiplication, addition and accumulation operations in Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) platforms. The second major issue is the computational complexity required for the effective solution of complex multi-dimensional problems either for scientific computation or for advanced graphical applications. Conventional algebraic techniques do not scale well in hardware terms to more than 3 dimensional problems, so a new approach is desirable to handle these situations. In this paper we describe scalable n-dimensional geometric algebra processor core architecture realizable using an FPGA or ASIC platform.