ACADEMIA

SANTA CLARA, CA -- NEC Electronics Inc. today announced the completion of its three-year system-on-a-chip (SoC) design environment initiative, code-named ACE-2, that significantly reduces the design cycle for complex SoC designs. The company met its goals for the program and expects customers employing the new design environment to dramatically reduce the time from system specification to tape-out for a 30-million-gate SoC. Customers can apply elements of this design methodology to current designs to reduce design time by up to two-thirds, while designers of next-generation ASIC SoCs will benefit from the methodology's system-level approach, as designs become increasingly complex and time-to-market advantages more essential. "Through the ACE-2 program, NEC Electronics has created a design flow that reduces design time and improves design productivity, predictability, flexibility and quality," said John Fallin, general manager, Design Execution Center, NEC Electronics Inc. "We have seen overall times reduced by up to two-thirds when the design flow is completely employed. By addressing design issues at the system level, we have created an environment in which SoC designers can fine-tune designs quickly and easily and still have time to focus on their key competencies, namely overall system design and software development." In addition to reducing hardware design time by up to two-thirds, designers using the ACE-2 environment can also realize up to ten-times faster verification speeds by performing simulation at the system level as opposed to the register transfer level. The design flow also delivers improved design predictability and flexibility by applying robust hardware verification, system analysis, quick behavioral synthesis and market segment-based design capabilities. Additionally, by employing system-level design techniques, NEC Electronics was able to reduce hardware and software description requirements by as much as 90 percent. About the ACE-2 Program NEC created the ACE-2 initiative to reduce turnaround time for ASIC SoC designs by up to two-thirds, from an average of 450 engineering months to fewer than 150 months. To realize the aggressive goals of ACE-2, NEC Electronics teamed with the world's leading electronic design automation (EDA) companies to define a new design methodology for quick and accurate SoC design. Phase 1 and 2 of the ACE-2 program included the development of tools necessary to support software design and verification, hardware verification, intellectual property modeling and design planning. The program also included the integration of performance analysis, hardware design, market-based hardware and software trade-offs and system analysis. Each of these capabilities reduces the time-to-market restrictions typically associated with deep submicron designs. Phase 3 focused on applying the design flow to confirm the "real world" capabilities of the ACE-2 methodology. The ACE-2 system-level environment complements NEC Electronics' comprehensive back-end design environment, OpenCAD®, comprising the industry's leading proprietary and third-party design tools. About NEC Electronics' SoC Strategy NEC Electronics offers its customers a path for continued, customized integration by providing a wide variety of standard products, application- specific standard products (ASSPs), application-specific custom products (ASCPs) and ASICs-depending on the customers' price, performance and time-to- market requirements. The products in NEC's SoC line-up can be customized for customer needs either immediately or in future generations. The ACE-2 design environment was developed to enhance NEC Electronics' ability to deliver on this promise, by enabling many of its standard products to be developed within the same design environment as its customers' ASICs-making the path to customization even more seamless and efficient.