ACADEMIA

ATLANTA, GA -- TeraCross, a provider of high-performance switch fabric integrated circuits, today announced the GLIMPS(TM)-1000 chipset -- a terabit switch fabric solution to be demonstrated live at SuperComm 2002 in Atlanta, GA. The GLIMPS(TM)-1000 chip set is a family of high-performance, cost-effective switch fabric elements specifically designed to meet the growing demands of bandwidth and intelligent services in next-generation switching systems. The GLIMPS(TM)-1000 supports high port densities with low latencies and Quality-of-Service (QoS) provisioning, implemented using a very low chip- count configuration. This approach yields a best-in-breed solution for a wide range of metro, core, and Storage Area Networks (SAN) applications. It also allows system designers to accelerate their development by reducing their integration time, while improving their market agility and time-to-market. "TeraCross has developed a unique fabric architecture that uses high density crosspoints to significantly reduce the number of components for a 320Gbps or higher capacity fabric card. By focusing on the scheduling problem, TeraCross offers a solution to reduce latency for systems under high loads of bursty traffic" says Jag Bolaria of the Linley Group. The GLIMPS(TM)-1000 easily interfaces to the next generation of 10G network processors. Using a SPI4.2 electrical interface with support of native SPI4.2, CSIX-L1 over SPI4.2, and NPF-SI logical signaling interfaces, the GLIMPS(TM)-1000 offers a quick and seamless interface to the latest and future high performance network processors. To assure easy integration between the network processor and switch fabric, the TeraCross TXQ devices have been undergoing co-simulation efforts with the Intel(R) IXP2800. These efforts will greatly facilitate interoperability between the devices and shorten customer development time significantly. "Customers demand interoperability in a multi-vender solution" said Doug Davis, general manager of Intel's Network Processor Division. "We have been working closely with TeraCross to assure a seamless interface between our fully programmable IXP2800 network processor and the TeraCross GLIMPS-1000 switch fabric solution. This will allow system designers to get to market quicker with reliable, high performance products for edge and metro/core applications". The GLIMPS(TM)-1000 Product Families The GLIMPS(TM)-1000 solution consists of two families of devices: the TXQ Queuing Chips and the TXS Scheduler Chips. The TXQ-1650 Queuing Chip resides on the line card. Its primary functions involve managing the on-chip Virtual Output Queuing (VOQ) memory, while providing an interface for both payload and control paths between the traffic manager or network processor and the fabric core. Each TXQ device supports one full-duplex 16Gb/s SPI4.2 interface for a network processor / traffic manager, thus requiring only one TXQ per line card for 10G of network bandwidth. The TXQ-1650 Queuing Chip support total system configurations of up to128 oc-192c or 10G ports and is implemented in a.18u CMOS technology. The TXS-1400 Scheduler Chip receives control information from the line card queuing chips, issues scheduling configuration commands to the TXQ Queuing Chips and the crosspoint subsystem, plus controls the flow of payload data traversing the crosspoint switches. A single TXS-1400 Scheduler supports systems of up to 64 oc-192c or 10G ports and is offered as an encrypted bit stream for a Xilinx Virtex-II FPGA. "We are pleased with TeraCross' decision to use Virtex-II(TM) FPGAs as the foundation for its GLIMPS(TM) scheduler," says Umesh Bhat, senior manager Partnerships at Xilinx. "This decision clearly demonstrates that Virtex-II(TM) FPGAs are the platform of choice for next-generation Intellectual Property being developed for high-performance networking systems." Complementing the TXS and TXQ devices are crosspoint switches and serializer-deserializer (SERDES) components. Through these proven, high-performance, carrier class devices, data packets traverse from ingress ports to egress ports. The result is a very low chip count solution that offers unparalleled performance, reliability, scalability, and interoperability built on low-risk building blocks. Using these building blocks, systems from 80Gb/s to terabit total bandwidths can easily be implemented. This is demonstrated in Teracross Development Systems (TDS-1000) which uses the recently announced 144x144 crosspoint switches from Mindspeed(TM). "The superior performance and low power of our crosspoint switches combined with TeraCross's breakthrough GLIMPS scheduler makes a natural choice for high-speed, high-density switching applications," said Babak Nabili, director of marketing for Mindspeed. "We are pleased to collaborate with TeraCross in enabling the terabit switching market." The GLIMPS(TM) Architecture The TeraCross GLIMPS(TM) architecture offers unprecedented low latency combined with inherent QoS provisioning for systems scaling to hundreds of ports, at data rates of 10 Gbps, 40 Gbps, and beyond. The core technology can easily scale to 5 terabits or more, while the first generation of products, the GLIMPS(TM)-1000, supports system of up to 1 terabit in capacity. The architecture's exceptionally low chip count and power consumption result in a compelling switch fabric solution that is ideal for high-end metro, SAN, and core system solutions. "The GLIMPS(TM)-1000 architecture was designed from the ground up to accommodate the need for a strong packet-scheduling engine in the presence of bursty, non-uniform traffic" says Kurt Busch, vice president of marketing for TeraCross. "The core scheduling algorithm addresses the requirements of all ports, while optimizing switching-decision processing to guarantee stringent performance goals. This assures low latency under high loads of bursty real-world traffic." TDS-1000 Development System TeraCross offers the TDS-1000 reference design, a terabit switch fabric evaluation platform for the GLIMPS(TM)-1000 chip set. Complementing the TeraCross devices are Mindspeed(TM) 144x144 high-speed crosspoint switches, a traffic generator, and line card interface modules to external network processors. Four TXQ line cards provide seamless interfaces to four full-duplex 10 Gb/s network processors / traffic managers, while the traffic generator emulates loads up to a 1 Tb/s of traffic through the system. A wide variety of traffic scenarios can be implemented using the traffic generator's flexible programmability features. To significantly reduce time-to-market, the TDS-1000 platform allows network processor software to be evaluated as part of a terabit fabric prior to integration into the customer's system. Pricing and Availability Samples of the TXS-1400 Scheduler are currently available as an encrypted bit-stream for Xilinx Vertex II FPGAs. The TXS-1400 is priced at $2000 each, in licenses of 1,000 units. Samples of the TXQ-1650 Queuing devices will be available in 4Q02 and will be priced at $300 each, in volumes of 1,000 units. The TXQ-1650 is packaged in a 676 pin BGA. TDS-1000 Development System is priced at $50,000 each and is also currently available. For more information visit www.teracross.com