ACADEMIA

The research group, led by electrical and computer engineering professor Xiuling Li, developed a technique to integrate compound semiconductor nanowires on silicon wafers, overcoming key challenges in device production. The team published its results in the journal Nano Letters.

Semiconductors in the III-V (pronounced three-five) group are promising for devices that change light to electricity and vice-versa, such as high-end solar cells or lasers. However, they don't integrate with silicon seamlessly, which is a problem since silicon is the most ubiquitous device platform. Each material has a specific distance between the atoms in the crystal, known as the lattice constant.

"The biggest challenge has been that III-V semiconductors and silicon do not have the same lattice constants," Li said. "They cannot be stacked on top of each other in a straightforward way without generating dislocations, which can be thought of as atomic scale cracks."

When the crystal lattices don't line up, there is a mismatch between the materials. Researchers usually deposit III-V materials on top of silicon wafers in a thin film that covers the wafer, but the mismatch causes strain and introduces defects, degrading the device performance.

Instead of a thin film, the Illinois team grew a densely packed array of nanowires, tiny strands of III-V semiconductor that grow up vertically from the silicon wafer.

"The nanowire geometry offers a lot more freedom from lattice-matching restrictions by dissipating the mismatch strain energy laterally through the sidewalls," Li said.

The researchers found conditions for growing nanowires of various compositions of the III-V semiconductor indium gallium arsenide. Their methodology has the advantages of using a common growth technique without the need for any special treatments or patterning on the silicon wafer or the metal catalysts that are often needed for such reactions.

The nanowire geometry provides the additional benefit of enhancing solar cell performance through greater light absorption and carrier collection efficiency. The nanowire approach also uses less material than thin films, reducing the cost.

"This work represents the first report on ternary semiconductor nanowire arrays grown on silicon substrates, that are truly epitaxial, controllable in size and doping, high aspect ratio, non-tapered, and broadly tunable in energy for practical device integration," said Li, who is affiliated with the Micro and Nanotechnology Laboratory, the Frederick Seitz Materials Research Laboratory and the Beckman Institute for Advanced Science and Technology at the U. of I.

Li believes the nanowire approach could be applied broadly to other semiconductors, enabling other applications that have been deterred by mismatch concerns. Next, Li and her group hope soon to demonstrate nanowire-based multi-junction tandem solar cells with high quality and efficiency.

The Department of Energy and the National Science Foundation supported this work. Other faculty involved in the project are materials science and engineering professors Jian-Min Zuo and John A. Rogers at the U. of I., and professor Cun-Zeng Ning, at Arizona State University. Jae Cheol Shin, a former postdoctoral researcher with Li, is the first author.