ACADEMIA

Appro has announced the Appro, Sandia and Intel collaboration for a “first of a kind” experimental cluster using the Appro next generation, Xtreme-X Supercomputer architecture. This system is based on Intel’s Knights Ferry (KNF) software development platform for the Intel Many Integrated Core (Intel MIC) architecture and will provide a platform to influence important Intel MIC architecture based scalable system designs.  Appro plans to showcase its next generation system at SC11 in Seattle - November 14-17.  Best practices session of this experimental cluster will be presented at the Appro booth #2312.

This collaboration was based on a common goal of helping Sandia National Laboratories to develop applications for current and future co-processor computational systems, develop new system software capabilities that can support the efficient movement of data to/from the cores in the Intel MIC/CPU heterogeneous compute node and to explore how the Intel MIC architecture can be used for implementations of alternative execution models for exascale computing.  This research project will enable better understanding of many-core performance issues and provide an excellent experimental foundation for the development of applications for this new class of platforms.  Sandia also would like to explore advanced system software and new programming models for heterogeneous compute nodes.

“We are excited to bring together Appro’s next generation supercomputer based on the latest Intel Xeon processor and Intel MIC architecture to be available for Sandia’s experimental cluster research project,” said Daniel Kim CEO of Appro.  “We are proud to collaborate with Intel on future technologies and Sandia’s research expertise to offer the most innovative supercomputing systems, so our industry can enjoy greater choice in processor technologies.”

Sandia’s Appro Xtreme-X Supercomputer consists of 42 nodes based on Mellanox QDR IB interconnect, delivered in a multiple rack-scale, heterogeneous node architecture and structured in three phases. Phase  one is the test bed platform based on the Intel Xeon 5600 processor and Intel’s Knights Ferry software development platform delivered by Appro  in September, 2011 as a baseline system for Sandia’s test work. Phase two is for the system to be upgraded to the future Intel® Xeon® processor E5 Family sometime in early 2012.  Phase three will be for the system to be further upgraded with pre-production Intel’s Knights Corner co-processors in 2012. In addition, Appro and Intel will provide the software and licenses required to support functionality of the heterogeneous node and full scale integrated system. This will include application development compilers, libraries and tools for the Knights Ferry platform. The contract between Appro and Sandia also calls for the delivery of a complete factory-integrated and pre-tested system with on-site maintenance services and next business day support response time.

"We are interested in research on next generation computer architectures and look forward to collaborating with Appro and Intel on our investigations of Intel MIC architecture”, said James Ang, Manager of the Scalable Computer Architectures department at Sandia National Labs. “This Knights Ferry cluster will support our exploration of advanced programming models like OpenMP and Intel Cilk Plus that map our current MPI applications to the Intel Xeon 5600 processor and Knights Ferry platform, and research into system software support for advanced data movement capabilities."

“Scaling for parallelism is fundamental to taking advantage of Intel’s multi and many core architectures,” said Joe Curley, Director of Marketing, Technical Computing Group at Intel. “This ‘first of a kind’ system will represent a leap forward in developing applications than can take advantage of current multi-core architectures and lead us into the many core era. The combination of Appro and Intel’s technical expertise in systems and compute architectures, along with Sandia National Laboratories’ knowledge of HPC applications, will allow users to take advantage of Intel Xeon processors and Intel MIC architecture to support future scientific research challenges.”

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