ACADEMIA

Open-Silicon announced that the company's Interlaken IP core has been used in over thirty implementations, and now includes silicon success in 28nm. The five generations of Open-Silicon Interlaken Controller IP have delivered to the market the high-performance necessary for leading networking devices. This scalable IP core offers a low risk solution that is proven across multiple foundries and process nodes. Open-Silicon's Interlaken IP, available as a standalone third-party IP core or as part of a customizable system and physical design solution, provides customers a quicker path to silicon.

According to a recently published report from Global Industry Analysts, Inc. (GIA), the information technology and communications (ICT) networking equipment/products market is expected to reach $214.2 billion by 2015. The market has been fuelled by the insatiable demand for bandwidth driven by multi-media applications, multiple users sharing a network, and more advanced PCs. Having recognized this trend early on, Open-Silicon developed the Interlaken IP core that has now been silicon proven in some of the most advanced process nodes.

"We found that our customers needed high-performance networking interface IP that was not available on the open market. Using our deep experience in integrating semiconductor IP, we developed the easiest-to-integrate ASIC Interlaken IP core with the highest-bandwidth for customers creating advanced networking products," said Aashish Malhotra, director of IP solutions, Open-Silicon. "As the Interlaken protocol has evolved to address additional applications, so has our IP core. We believe that offering the lowest risk solution, that meets the Interlaken Alliance's released specification will allow the industry to make a smooth transition to 100Gbps applications and beyond."

About the ASIC Interlaken IP CoreDeveloped to incorporate of the benefits of the popular SPI4.2 and XUAI interfaces, Interlaken is a scalable protocol for chip-to-chip packet transfers. High-bandwidth applications, such as those required in networking devices, can utilize the Interlaken protocol to build on the channelization and per channel flow control features of SPI4.2, while also reduce the number of chip I/O pins by using high-speed SerDes technology. Interlaken as a protocol had transitioned from the original chip to chip interconnect between the network processor and traffic manager to other applications like the extensions to support Interlaken Look Aside as the interconnect for external memory interfaces. Open-Silicon's Interlaken IP can scale from 10Gbps to over 300Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 12.5Gbps) and a variable number of SerDes lanes (1 to 24). This scalability makes Interlaken ideal for multiple generations of future network switches, routers and storage equipment.