ACADEMIA
Workshop on Programming Massively Parallel Processors offered July 10
The National Center for Supercomputing Applications (NCSA / www.ncsa.uiuc.edu) and the Institute for Advanced Computing Applications and Technologies (IACAT / www.iacat.uiuc.edu) will present a Workshop on Programming Massively Parallel Processors (PMPP) on July 10, 2008 in Urbana-Champaign, Illinois. 
Until recently, computer performance improvements were largely driven by the ever-increasing clock speed of commodity microprocessors. As semiconductor devices shrink to enable higher clock rates, poor wire scaling becomes the performance-limiting bottleneck. In order to take advantage of the shrinking transistor size and alleviate the poor wire scaling, manufacturers resort to placing multiple copies of the same design on a single die instead of increasing the clock speed. Multi-core chips, unheard of just a few years ago, are a standard today. While general-purpose processors are still restricted to just a few cores per die, more specialized chips contain hundreds of smaller well-tuned SIMD-enabled cores capable of running thousands of execution threads. The workshop will bring together researchers, industry, and users concerned with the issue of programming multi-core and many-core architectures for productive use in applications ranging from desktop to high-performance computing systems. The workshop will include presentations from industry leaders and early technology adopters and will stimulate the dialogue among researchers about programming models, languages, and tools that the community is lacking in order to take advantage of the emerging multi-core and many-core architectures. Topics will include:
* Novel chip multiprocessing architectures * Programming models for massively parallel processors, algorithms, and formal methods * Programming languages for multi- and many-core systems, compilers and tools * Applications running on multi- and many-core systems PMPP will be co-located with the 2008 Reconfigurable Systems Summer Institute (RSSI / www.rssi2008.org), but participants must register separately for the two events. More information on PMPP, including online registration, is available at its Web site.
Until recently, computer performance improvements were largely driven by the ever-increasing clock speed of commodity microprocessors. As semiconductor devices shrink to enable higher clock rates, poor wire scaling becomes the performance-limiting bottleneck. In order to take advantage of the shrinking transistor size and alleviate the poor wire scaling, manufacturers resort to placing multiple copies of the same design on a single die instead of increasing the clock speed. Multi-core chips, unheard of just a few years ago, are a standard today. While general-purpose processors are still restricted to just a few cores per die, more specialized chips contain hundreds of smaller well-tuned SIMD-enabled cores capable of running thousands of execution threads. The workshop will bring together researchers, industry, and users concerned with the issue of programming multi-core and many-core architectures for productive use in applications ranging from desktop to high-performance computing systems. The workshop will include presentations from industry leaders and early technology adopters and will stimulate the dialogue among researchers about programming models, languages, and tools that the community is lacking in order to take advantage of the emerging multi-core and many-core architectures. Topics will include:
* Novel chip multiprocessing architectures * Programming models for massively parallel processors, algorithms, and formal methods * Programming languages for multi- and many-core systems, compilers and tools * Applications running on multi- and many-core systems PMPP will be co-located with the 2008 Reconfigurable Systems Summer Institute (RSSI / www.rssi2008.org), but participants must register separately for the two events. More information on PMPP, including online registration, is available at its Web site. 
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