CLOUD

Alliance Semiconductor Corporation, a worldwide provider of analog and mixed signal products, high-performance memory products, connectivity and networking solutions for the communications, computing, embedded, industrial and consumer markets, today announced the availability of its extensive family of IEEE 1149.1 compliant JTAG devices. These products provide very efficient solutions to implement design-for-test (DFT) on the PCB for the networking, communications, storage, compute and embedded systems. Alliance’s JTAG products allow leading OEM partners to develop highly integrated IEEE 1149.1 test strategies at the board, system and sub module levels. The integration of Alliance’s JTAG products enable system engineers to reduce Flash memory and CPLD/FPGA programming time, while providing higher fault coverage and system diagnostics in the factory and the field. “Our JTAG products were designed to meet the growing design-for-test requirements of system engineers and the paradigm shift in the industry towards standardizing on JTAG as the primary board and system test technology. They enable structured PCB designs, maximize PCB test coverage and minimize PCB test time so that our customers can debug, test and deploy new designs to market faster,” said Robert Napaa, vice president of marketing for Alliance’s System Solutions business unit. “With the high capital costs associated with traditional testing methods, our JTAG products further strengthen our commitment to providing the most efficient and cost-effective solutions. The expansion of Alliance’s system solutions offering with JTAG products also enables us to provide customers with more complete systems control and support.” Alliance’s family of JTAG products includes four devices: a 3-port JTAG gateway, a 6-port JTAG gateway, a JTAG test controller and a JTAG test sequencer. The 3-port and the 6-port JTAG gateways allow a long JTAG chain to be sub-divided into three or six smaller chains. This provides isolation between the various components on the chain and speeds the access time to the devices. The JTAG test controller has a generic CPU interface to allow the host or the software to control the JTAG chain. This is critical for quick fault isolation and system debugging. The JTAG test sequencer has a Flash interface. It executes JTAG tests stored into Flash by running them through the JTAG chain and comparing the results. Depending on the system requirements, any combination of the four devices can be used. Alliance’s JTAG products offer a multitude of benefits and features to system engineers, including: • Enables the addition of new silicon devices without the risk of rendering PCB untestable • Total PCB diagnostics upon power up with the use of BIST within ICs • Enables the ability to diagnose interconnect faults on the back plane of the sub rack between cards • Allows the ability to address cards in a sub rack via software, no jumpers required to maintain JTAG chain integrity • JTAG chain partitioning of a single large chain into multiple addressable JTAG chains • Reduces time needed to program FLASH memory with chain partitioning • Ability to update FLASH and CPLD contents without PCB removal from the system • Aids fault diagnosis, a single fault on the JTAG chain does not render the card completely untestable