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SAN FRANCISCO, CA -- Power X Networks(TM) today announced details of their next-generation switch fabric architecture that will enable the highest levels of system reliability and Quality of Service for next-generation advanced networking systems. Building on the success of the first generation award-winning Star(TM) family chip set, Power X's new Tera(TM) family adds features such as embedded memory for input buffering and output queuing, superior packet resiliency, and fully scalable system architecture. The Tera Family will support both OC-48c and OC-192c line rates at wire speed from 32 to 128 ports for an aggregate full-duplex bandwidth of 320Gbps scalable to 1.28Tbps. "The switch fabric is a key element that defines the QoS capability and reliability for a networking system," said Linley Gwennap, principal analyst at The Linley Group. "Power X's Tera Family delivers these elements and is an innovative extension to a proven, successful switch-fabric architecture." System Reliability One of the most important system functions addressed in the Power X's Tera Family architecture is enhanced packet reliability. As 10Gb line rates become more pervasive, the implementation of switching data error-free across the fabric backplane becomes much more challenging. Power X's Tera Family chip set guarantees true lossless operation across the backplane with a unique feature called Reliable Delivery Protocol (RDP). RDP is a continuously running low-level protocol that ensures data cells have been received at the egress correctly and without corruption. RDP operates within the Tera Family architecture at all packet sizes at wire speed, a Power X differentiator and industry first. The Tera Family architecture will include provisions for enhanced fabric and line card redundancy. The architecture to configured to enable N+ 1 line card redundancy, allowing upgrades on live systems and minimizing the amount of overhead implemented within network processors to service a failed line card. In addition the Tera Family will support multiple fabric redundancy schemes which, when combined with RDP, guarantee a truly lossless fabric fail over. Each of these enhancements will provide designers of networking equipment greater flexibility as they analyze the cost-to-performance tradeoff in providing critical system reliability. "We are very pleased to expand our product offering and build on the success we have demonstrated with our first-generation switch fabric technology," stated Phil Mercer, chief executive officer at Power X Networks. "Our approach with Tera Family will let Power X's customers deliver unprecedented levels of provisioning functionality while enhancing system reliability, ultimately leading to additional revenue opportunities for their service provider customers." Quality Of Service In 2001, Power X ramped the Star Family switch fabric chip set into production. This chip set deliverers unsurpassed intelligent service provisioning by implementing a patented hierarchical, or two-level, arbitration and weighted bandwidth allocation scheme supporting 16 traffic classes per port. Adding to the ability to provision bandwidth per-class and per-connection at wire speed, the Tera Family will support strict priority or weighted round-robin scheduling for each port. Strict priority will enhance performance of time-critical applications such as Voice over IP (VoIP) by maintaining a minimal and consistent latency through the fabric. Flexible System Architecture The Tera Family further implements innovative embedded 2.5Gbd serial links that provide a core overspeed from 2.4x up to 3.2x. The SerDes links include a self-alignment feature easing the design of back planes by allowing variable length high-speed data traces on the printed circuit board. In addition, power and performance are easily optimized for each application by programming the numbers of serial links used and configuring the sizes of Virtual Output Queues (VOQs). Scalability is built into the Tera Family architecture by allowing users to replace OC-48c line cards with OC-192 line cards as bandwidth demand increases. This provides a cost effective means to evolve the bandwidth of the system without requiring a complete system redesign. In addition, this architecture will allow reuse of OC-192c line cards as core fabric is increased to 640 Gbps or 1.28Tbps. Finally, as a founding member of the CSIX consortium, Power X maintains its commitment to industry standards by adopting Network Processing Forum interface specifications. This gives system designers options to interface the Tera Family with industry-leading CSIX-compatible network processors available on the market. This best-of-breed approach allows designers to optimize their chip set for their specific application. For more information visit www.powerxnetworks.com