DEFENSE

Acceleration Card, HyperTransport Technology Interface IP, Complement C-to-FPGA Compiler to Enable Order of Magnitude Performance Improvements: Celoxica, a member of the HyperTransport Technology Consortium, today announced availability of the first complete off-the-shelf hardware and software compiler design bundle for High-Performance Computing (HPC) using industry standard HyperTransport (HTX) slots. The HTX bundle combines an intellectual property (IP) core for HTX compliant connectivity, an FPGA-based HTX acceleration card and a comprehensive software-programming environment. The solution, part of Celoxica’s family of Accelerated Computing products, enables algorithm acceleration using FPGA based co-processing and high bandwidth HyperTransport technology communications in computing systems with AMD OpteronTM processors. The Celoxica RCHTX acceleration card includes two Xilinx Virtex 4 FPGA devices, 24 MB of dedicated QDR SRAM, and a range of I/O. The main co-processor FPGA is a high density 16 million gate device that can be reprogrammed by the user to accelerate compute intensive algorithms. The second FPGA is configured as a bridge, containing an HTX IP core developed and licensed by Celoxica. This bridge FPGA and IP provide the HyperTransport interconnect between the FPGA co-processor and the entire host processor system and memory space. Enabling the HTX solution, Celoxica’s DK Design Suite delivers an IDE and compiler for software programming of the FPGA co-processor. DK allows HPC programmers to use familiar software languages and legacy code in the development of hardware accelerators. Celoxica’s technology compiles high-level, C-based code directly to the user FPGA device, eliminating the need to recode complex and proprietary algorithms into a low level hardware description language. A board support package (BSP) and software API is provided for the RCHTX card to further streamline the design flow. As demands drive datacenter growth and complexity, HPC systems (supercomputers and clustered servers) are continuously being pressed to deliver higher compute performance within power and space constrained environments. The low latency, high bandwidth interconnect provided by HyperTransport technology coupled with Celoxica’s software programming environment for FPGA hardware enables HPC programmers to exploit FPGAs as parallel co-processors that deliver orders of magnitude higher performance with little or no impact on existing power and floor space budgets. "Three things have opened the door to making FPGA co-processing a reality today: the continued size and speed improvements of FPGA silicon; the availability of high-bandwidth interfaces such as HyperTransport technology; and, the advent of reliable compiler technology from software code directly to FPGA hardware," said Jeff Jussel, vice president of marketing and general manager of the Americas for Celoxica. "Today, customer benchmarks demonstrate that our Accelerated Computing solutions deliver massive performance/power advantages for a wide range of compute intensive applications." "HyperTransport technology and AMD64 technology with Direct Connect Architecture can provide a tightly coupled co-processor expansion capability and address the communications bottleneck that has negatively impacted compute off-load to coprocessors in other solutions," said Mike Goddard, Director, Advanced Technology Planning and Performance Labs, AMD. "Coupling this with an easy-to-use programming environment, integrated card solution, IP and advances in FPGA technology makes this a successful example of Celoxia’s valued support of AMD’s Torrenza initiative." Celoxica’s HyperTransport technology solution complements its existing Accelerated Computing products, which provide compiler and hardware interface support to enable FPGA-based co-processing for a wide range of HPC solutions. Celoxica’s RCHTX card is priced at $15,000 in single quantities and along with Celoxica compiler and HTX interface is available for immediate delivery.