Celoxica Inks Agreement with Czech Academy of Sciences

Celoxica is working with the Academy of Sciences of the Czech Republic (ASCR) to accelerate the wide-scale deployment of high-performance reconfigurable computing and programmable logic implementations of next-generation digital-signal processing applications. Under a multi-year research agreement with the Academy's Institute of Information Theory and Automation (UTIA), Celoxica and UTIA will develop the complex mathematical models and calculations that underpin the deployment. The agreement is a dividend of the long history of successful collaboration and partnership between Celoxica and UTIA. The promise of high-performance reconfigurable computing is finally being realized on a commercial scale through a combination of unrelenting advances in lower power, extreme performance programmable logic architectures and the new software programming paradigm, characterized by electronic system level (ESL) design, that enables these architectures to be more easily exploited and integrated into high-performance computing (HPC) infrastructures and systems. Working with industry, Celoxica is already deploying its award-winning ESL design solutions and acceleration cards to enable HPC and DSP designers take maximum advantage of the parallel processing capabilities of FPGA, either as software-programmable custom processors or co-processors that augment existing solutions such as high-end DSP or microprocessor technology. The research agreement with UTIA will help accelerate the development of Celoxica's next generation solutions. "Our continued program of invention and innovation requires continued investment and we have carefully selected UTIA as a long-term research partner to augment our internal R&D efforts," said Phil Bishop, president and CEO of Celoxica. "The team at UTIA brings a wealth of knowledge, expertise and creativity that will help us develop solutions that further push the boundaries of accelerated computing and next generation programmable logic design." Jiri Kadlec, head of signal processing and distinguished researcher in reconfigurable signal processing technology, commented, "There is now commercial recognition of how massively parallel, reconfigurable hardware processing architectures can be practically used to solve some of the issues that surround complex computing problems. Our research has helped define the solutions to these problems and with the availability of software programmable hardware we can now focus effort on the underlying mathematical calculations that will drive commercial applications."