ENTERTAINMENT

High Performance Data Path Acceleration Architecture in New P1 and P2 Processors Boosts Performance, Lowers Costs and Delivers Optimal Scalability.

Freescale Semiconductor introduces three new QorIQ processors, which for the first time incorporate the company’s advanced Data Path Acceleration Architecture (DPAA) programming model into QorIQ P1 and P2 level multicore products. The introduction of the P1023/1017 and P2040 communications processors extends Freescale’s DPAA technology to all QorIQ platform levels, spanning single-core to eight-core products and across frequencies from 400MHz to 2.2 GHz.

The common DPAA software architecture allows customers to develop code for one QorIQ processor and easily scale it up or down throughout the QorIQ family, dramatically shortening development cycles. It also allows customers to create extremely flexible end products which offer a broad range of cost and performance points.

“Offering DPAA across the QorIQ family helps our customers apply software developed for existing QorIQ products to our P1 and P2 level QorIQ offerings, thereby optimizing software investments and reuse,” said Preet Virk, director of strategic marketing for Freescale’s Networking Processor Division. “These new QorIQ products give our customers the flexibility, scalability and performance required to manage rising IP traffic rates while keeping price points extremely competitive.”

The P1023/P1017 are highly integrated dual- and single-core devices which are ideally suited for high performance 802.11N wireless LAN access points, SMB gateways and low-end fixed routers. Key advantages include low power consumption to meet Power over Ethernet requirements, three PCI Express controllers to support three radio solutions, datapath offload for optimized performance of enterprise WLAN access points, and Freescale’s advanced security co-processor that offloads protocol processing for encryption algorithms.

The P2040 is a cost- and power-optimized quad-core device enabling market leading performance and functionality for solutions such as fixed routers, Long Term Evolution (LTE) channel cards and enterprise security applications. In addition to the DPAA that offloads common packet-handling tasks, the P2040 supports flexible SerDes configurations to minimize glue logic required, and includes embedded hypervisor technology, which enables each core to run its own operating system independent of the other cores, thus providing true hardware partitioning and virtualization.

The QorIQ DPAA offloads select tasks from the primary processing cores, allowing the cores to perform higher-value tasks or to achieve application performance targets at lower frequency, cost, and power. The DPAA consists of the Frame Manager which implements policing, classification, and scheduling over Ethernet ports; the Queue Manager which performs queuing, congestion control, workload distribution and packet ordering; the Buffer Manager which assigns packets to buffers to minimize memory consumption; the Security Block for implementing crypto algorithms, and the Pattern Matching Engine to search for text strings in packets for unified threat management.

Freescale offers a single application programming interface (API) to access the DPAA, along with common GUI-based configuration tools and example framework applications that set up the DPAA infrastructure. The DPAA achieves near-linear scaling as additional cores are applied to a task.

P1023/1017 product features

• Dual (P1023) and single (P1017) e500 Power Architecture cores running up to 800 MHz
• DDR3/3L memory controller
• Open-PIC interrupt controller
• High speed interconnects including 16-bit enhanced local Bus supports booting from NAND flash memory, USB 2.0 controllers. Host/Device support via ULPI, SPI controller supporting booting from SPI serial flash memory, and PCI Express
• Data Path Acceleration Architecture
• 45nm SOI process technology for low power implementation
• Sub-5W power
• 457-pin WB TePBGA 1, 19mm x 19mm package

P2040 product features

• Quad e500mc Power Architecture cores running up to 1.2 GHz
• 1 MB shared CoreNet platform cache w/ECC
• DDR3/3L SDRAM memory controller with ECC support running up to 1200 MHz
• High speed interconnects including 3 x PCI Express, Serial RapidIO (1.3 + 2.1) with Type 9 and 11 messaging, and 2 x SATA 2.0
• CoreNet Switch Fabric
• Five Ethernet controllers
• Data Path Acceleration Architecture
• 45nm SOI process technology for low power implementation
• Sub-8W power
• 783-pin package, 23x23mm, 0.8mm pitch package

Development tools

Comprehensive hardware and software development kits are planned for the portfolio, including a Linux BSP, a software development tool kit and CodeWarrior enablement technologies. Freescale plans to announce a series of reference designs based on the new products in Q1 and Q2 of 2011.

Availability and pricing

The P1023/17 are planned for sampling in Q1 2011, and P2040 alpha samples are planned for Q1 2011.