GOVERNMENT
Synopsys Physical Synthesis Integrated Into NEC's Hierarchical Design Flow
MOUNTAIN VIEW, CA -- Synopsys, Inc. (Nasdaq:SNPS), today announced that its Chip Architect and Physical Compiler(TM) products have been integrated into NEC Corporation (NEC) (Nasdaq:NIPNY) hierarchical design flow, enabling the completion of a five-million gate, 166 MHz multimedia LSI, using NEC's 0.13-micron process. Following a series of engagements, NEC has decided to deploy Chip Architect and Physical Compiler(TM) into NEC's new hierarchical design flow in the company's design centers worldwide. This deployment will provide for complex multi-million SoC design implementation on NEC's advanced silicon technology, CB12 (0.13-micron process) and below. "NEC understands that supporting a design environment which scales to larger complex designs is the most important design factor in meeting customer requirements," said Yoshitada Fujinami, chief manager of System LSI Design Engineering Division, NEC Corporation. "By designing a five-million gate, 166 MHz multi-media LSI using NEC's 0.13-micron process with Synopsys' Physical Synthesis hierarchical design flow, we have confirmed that this new methodology delivers not only scalability, but also the best timing convergence we have ever experienced. Based on this and other successes, NEC has decided to use Chip Architect and Physical Compiler(TM) as the main part of our new hierarchical design flow." NEC relied on Chip Architect for design planning and analysis before using Physical Compiler for synthesis and placement. NEC established their full-chip timing closure methodology using Physical Compiler for both block- and chip-level timing closure. "NEC's leading edge silicon technology and long history of successful implementation of complex ASICs has made them an industry leader," said Sanjiv Kaul, senior vice-president and general manager for Synopsys Physical Synthesis business unit. "NEC's choice of Synopsys Physical Synthesis as the core of their standard 0.13-micron, hierarchical methodology is a strong endorsement of this technology." For more information visit www.synopsys.com