GOVERNMENT

HSIN-CHU, TAIWAN -- Taiwan Semiconductor Manufacturing Company (TSMC) (NYSE:TSM) today announced Reference Flow Release 2.0, the foundry industry's most comprehensive Reference Flow for advanced IC design. The new flow combines physical synthesis and physical optimization methodologies with a more comprehensive static timing analysis hand-off procedure, comprehensive RC and delay correlation capabilities and technology files, and an improved antenna fixing guideline for improved manufacturability. "TSMC's Reference Flow Release 2.0 is far more than simply a set of EDA tools; it is a highly integrated set of methodologies for designers using TSMC's technology. Reference Flow Release 2.0 provides greater design efficiency, better chip performance, and increased first-pass silicon success," said Dr. Ping Yang, Vice President of Design Services for TSMC. "These benefits are the result of several key improvements, including a more powerful timing closure capability, a streamlined interface between timing analysis and timing-driven implementation, more sophisticated antenna fixing, and better correlated RC and delay between each design tasks," he said. Physical Synthesis and Physical Optimization TSMC Reference Flow Release 2.0 shortens design cycles by combining a new physical synthesis methodology with powerful physical optimization techniques for more efficient timing closure. Comprehensive Static Timing Analysis Hand-Off The new static timing analysis hand-off procedure boosts productivity by including a utility which efficiently converts timing constraints to streamline the interface between timing analysis and timing-driven implementation phase. In addition, improved timing verification coverage also helps designers achieve optimal timing targets for better design quality. Comprehensive RC and Delay Correlation TSMC Reference Flow 2.0 improves overall design manufacturability with RC and delay correlation that runs from silicon through 3D solver, RC extraction, placement and routing, through to physical synthesis. A set of well-correlated technology files, based on TSMC's 0.15-micron library, has also been included as part of the Reference Flow deliverables. These features are expected to increase first-pass silicon success. Power Handling and Antenna Rule Fixing Improved first pass silicon success also comes from the new power handling guidelines, including power grid analysis, which is key to avoiding IR drop and electromigration issues. In addition, Reference Flow 2.0 features a major enhancement for antenna rule fixing. To shorten antenna fixing run-time, as well as eliminate discrepancies between the routing and the design rule check (DRC) phases, TSMC provides guidelines for proper ratio limit setting and a new antenna model extraction methodology that improves the handling of sub-blocks in the hierarchical design. TSMC Reference Flow Release 2.0 is available now to existing customers through TSMC Online, the company's web-based eFoundry resource center. Also included with the Reference Flow are numerous application notes, guidelines, scripts, utilities, makefiles and training materials and tutorials. For additional information visit www.tsmc.com