INDUSTRY

Intelligent bridge reduces development time for wireless infrastructure, storage,and embedded system applications: Mercury Computer Systems announced its Serial RapidIO-to-PCIe Bridge IP (intellectual property) Core -- the first intelligent bridge of its kind in the industry. The Serial RapidIO-to-PCIe intelligent bridge features complete protocol translation, an optimized dual-channel multi-threaded DMA engine, and a pipelined PCI Express-to-RapidIO mapping table to address high-throughput streaming applications as both consumer and producer. It also provides a variety of system service features including mailbox message queueing, PCIe MSI/MSI-X interrupt controller, RapidIO-to-PCIe Atomic transaction encapsulation, access protection, real-time event counters, and error management. "Interworking has always been a priority in the development of the RapidIO standard, and increasingly we see a demand among engineers to enable bridging to a variety of standards-based interfaces," said Tom Cox, Executive Director of the RapidIO Trade Association. "With Mercury's new bridging IP, these designers can take advantage of Serial RapidIO system-level capabilities while leveraging existing devices such as multicore processors, network processors, and FPGA-based computational elements." Over the last two years, Mercury has established itself as the leading provider of system-level IP for Serial RapidIO interfaces, and has successfully demonstrated IP working in a range of silicon technologies, including FPGA, structured ASIC, and ASIC implementations. "This is a natural fit for a variety of applications in wireless infrastructure, storage, and embedded systems," said Tracy Richardson, Director of the Silicon Solutions Group, for the Advanced Solutions business at Mercury. "Mercury's intelligent bridge IP core enables connectivity between processors that have only PCIe buses, to Serial RapidIO interfaces on DSPs from Freescale and TI, and Serial RapidIO switch fabrics from many vendors including Mercury." The Serial RapidIO-to-PCIe Bridge IP Core is architected for applications that require high-bandwidth bridging between PCI Express devices and Serial RapidIO fabrics and devices. It bridges a 4X serial RapidIO port, operating up to 3.125 GHz, to an 8X PCI Express port operating at 2.5 GHz, through an intelligent non-transparent bridge. With the rapid growth in the Serial RapidIO ecosystem, there is a requirement to co-exist and connect to existing buses such as PCIe -- the Mercury Serial RapidIO-to-PCIe Bridge IP core fills that need. There is also considerable demand from designers to bridge from Serial RapidIO to other interface standards, and Mercury supports those applications with a comprehensive design service and IP portfolio. Mercury intends to leverage its relationships with several leading semiconductor technology suppliers to provide the bridge as either an FPGA netlist that will be supported by Altera, Lattice, and Xilinx FPGAs; pre-programmed FPGAs; or license the IP for ASIC or FPGA environments. The Mercury Serial RapidIO-to-PCIe Bridge IP Core is available now. For more information, visit its Web site or call 866-627-6951. Pricing information is available by contacting Mercury at SiliconIP@mc.com.