INDUSTRY

Intel Corporation today announced the appointment of two individuals to the position of Intel Senior Fellow and four individuals to the position of Intel Fellow. The new Senior Intel Fellows are Stephen S. Pawlowski and Ian A. Young. The new Intel Fellows are Boris A. Babayan, Timothy L. Deeter, Albert Fazio and Shiuh-Wuu Lee. The title of Intel Senior Fellow represents the highest level of technical achievement within the company. Intel created the position of Senior Fellow in 2002 to recognize the most senior and influential Intel Fellows. Intel recognizes sustained outstanding technical achievement with the title of Intel Fellow. An Intel Fellow title is equivalent to that of an appointed vice president. Intel Senior Fellows Pawlowski, 45, is the chief technology officer and director of platform planning, architecture and technology in the Enterprise Platforms Group (EPG). Pawlowski joined Intel in 1982 and was appointed Intel Fellow in 2000. He currently leads EPG's efforts to plan and design products that provide competitive advantage at the both the component and platform levels. He led the design of the first multi-bus/single-board computer based on the Intel386(TM) processor and has been a lead architect or designer for several key PC and server technologies including the system buses for Pentium(R) III and Pentium 4-based PCs, the system architecture for servers based on Itanium(R) processors and the 82450 GX and NX server chipsets. Pawlowski holds 52 patents in the area of system and microprocessor technologies. Young, 53, is director of advanced circuits and technology integration in the Technology and Manufacturing Group. Young joined Intel in 1983, was appointed Intel Fellow in 1995 and is responsible for defining and developing circuit designs and optimizing manufacturing process technology for high-performance microprocessors and communications products. He developed the original Phase Locked Loop-based clocking circuit for the 50 MHz Intel486 processor and subsequent generations of clocking circuits through the 3 GHz Pentium 4 processor. More recently, he has lead development of communications technologies, including a CMOS 10Gb/s multiplexer chip for optical networking and a CMOS RF radio transceiver chip for wireless LANs. He holds 36 patents. Intel Fellows Babayan, 70, is director of architecture in the Software and Solutions Group. Babayan joined Intel in 2004 and leads worldwide development efforts related to compiler technologies for Intel server products, technologies that enable applications to run on multiple computer architectures without recompiling, as well as Intel security technologies. He has led the teams that build supercomputers for the former Soviet Union and holds 11 U.S. and five Russian patents. Deeter, 52, is director of design rules and tapeout technology in the logic technology development group, part of the Technology and Manufacturing Group. Deeter joined Intel in 1981 and is in charge of developing the parameters governing the physical design of microprocessors. He has been involved in specifying design parameters and validation methodologies for every Intel microprocessor technology since 1985. He holds five patents. Fazio, 43, is director of memory technology development in the Technology and Manufacturing Group. Fazio joined Intel in 1982 and is responsible for exploring and developing flash memory and multi-level cell memory technologies as well as novel memory technology ideas. He was responsible for the development of the Intel StrataFlash memory and has been involved in a number of other memory development programs at Intel including SRAM, EPROM and NVRAM. He holds 24 patents. Lee, 56, is director of advanced circuit simulation computer-aided design (CAD) in the Technology and Manufacturing Group. Lee joined Intel in 1987 and currently leads research and development of CAD technologies used to design Intel products. Before joining Intel, Lee served as a member of the technical staff at AT&T Bell Labs. He has initiated development of a number of leading CAD tools used to address difficult chip design challenges. He has authored 39 technical articles and conference presentations.