INDUSTRY

Bringing the next higher density networking memory to market, Toshiba America Electronic Components, Inc. (TAEC) and its parent Toshiba Corp. (Toshiba) today announced development of a series of 512 megabit(1) (Mb) Network Fast Cycle RAMs (FCRAM) with a minimum random cycle time of 22.5 nanoseconds (ns), the fastest random cycle time yet achieved in FCRAM1. The new devices are dedicated to supporting high performance network applications, including switches and routers in network systems. Toshiba's Network FCRAMs incorporate enhanced DRAM technology to achieve a large memory capacity and random access time rivaling the speed of SRAM. Narrowing the active memory area achieves low power consumption and a random cycle time performance more than double that of present DRAM. "Our new line up of 512Mb FCRAM1 devices provide a selection of interfaces, speeds and organizations to meet the needs of the growing number of customers that are designing network equipment with Network FCRAM," said Scott Beekman, business development manager, communication memory products, for TAEC. "With double the density, random cycle times down to 22.5ns, and data transfer rates up to 533Mbps, these new network FCRAM1 memory devices provide a significant improvement in performance with a wide selection of features for design flexibility." Toshiba currently manufactures Network FCRAM1 and FCRAM2 in 256Mb and 288Mb densities respectively. Now, 512Mb Network FCRAM1 is available to expand the product offering. Toshiba Network FCRAM2 in 576Mb density, designed to support parity bits for error correction, is scheduled to be available in 2005. The specification of Toshiba's Network FCRAM(TM) is fully compatible with Samsung's Network-DRAM(TM). Toshiba and Samsung will discuss standardization of the next generation Network FCRAM, scheduled for commercialization in 2005, with a planned operating frequency of over 400MHz. Samples of the new memories are available now, with mass production slated for the third quarter of 2004, at a few hundred thousand units a month. Toshiba 512Mb FCRAM1 Product Line Up Interface P/N (x8 I/O) P/N (x16 I/O) Data Random Random Transfer Cycle Access Rate Time Time (max.) (min.) (max.) SSTL_18 TC59LM906AMG-37 TC59LM914AMG-37 533Mbps 22.5ns 22.0ns HSTL TC59LM906AMG-45 TC59LM914AMG-45 444Mbps 25.0ns 22.0ns TC59LM906AMG-50 TC59LM914AMG-50 400Mbps 27.5ns 24.0ns SSTL_2 TC59LM905AMG-50 TC59LM913AMG-50 400Mbps 25.0ns 22.0ns TC59LM905AMG-55 TC59LM913AMG-55 364Mbps 27.5ns 24.0ns TC59LM905AMG-60 TC59LM913AMG-60 333Mbps 30.0ns 26.0ns Products listed above are available in BGA packages designed to comply with European Directive 2002/95/EC on the restriction of the use of certain hazardous substances, including lead. Contact your TAEC sales representative for products in traditional BGA packages. Major Features of the New Products 1. Fast random cycle time of 22.5ns is now available in 512Mb density. Also, data transfer rates up to 533Mbps with 266MHz clock. 2. Designed to maintain backward compatibility with 256Mb density Network FCRAM1. 3. Product line-up achieves performance boost with an 8-bank organization, and maintains compatibility with 4-bank devices. 4. Variable write data length control and only one clock cycle bus turnaround time. 5. Write/Read data strobe (Bi-directional DQS) is compatible with DDR1 SDRAM. Bi-directional differential DQS, compatible with DDR2 SDRAM, is available in the TC59LM906AMG device. 6. Three types of interface, SSTL_2, SSTL_18 and HTSL, are supported. SSTL_2 is compatible with 256Mb Network FCRAM1 and DDR1 SDRAM. SSTL_18 is compatible with DDR2 SDRAM. HTSL is used in HSSRAM, and this interface makes it easy for designs to migrate from HSSRAM to FCRAM. 7. Package is 60ball mBGA (16.5mm x 12.7mm, 1.0mm x 1.0mm ball pitch). 8. Programmable Driver Strength by Internal Mode Registers. Three steps for SSTL_2 interface products and four steps for SSTL_18 interface products. Simulation Model The new Network FCRAM devices are supported by advanced simulation models jointly developed by Toshiba and Denali Software Inc., the leading supplier of tools and technology for memory system design and verification. These simulation models are delivered on Denali's Memory Modeler AV platform and can be used with commercial Verilog and VHDL simulation environment to facilitate and accelerate Network FCRAM design-in activity. Network FCRAM models are available immediately from Toshiba at: (URL: https://www.toshiba-semicon.jp/cgi/web/memory/sm.htm) and Denali Software at: (http://www.ememory.com/Toshiba-FCRAM). Denali Software, Inc. is the leading provider of electronic design automation (EDA) tools and intellectual property (IP) for chip interface design and verification. (URL: http://www.denali.com/) Specifications of the New Products Product 512Mb Network FCRAM (Double Data Rate Fast Cycle RAM) Process 0.13um CMOS Organization 8-bank x 8M words x 8bits 8-bank x 4M words x 16bits Power Supply Voltage 2.5V+/-25V Interface SSTL_2 (VddQ min=2.3V, VDDQ max=VDD) SSTL_18, HSTL (VddQ min=1.4V, VDDQ max=1.9V) Package 60ball mBGA (15x4, 1.0mm x 1.0mm ball pitch) Write/Read Data Strobe Bi-directional DQS Also, Bi-directional differential DQS supported by x8 and SSTL_18 Product, TC59LM906AMG Write/CAS Latency (WL) CL-1 Read/CAS Latency (CL) 3 and 4 for SSTL_2 products 3, 4 and 5 for SSTL_18/HSTL products Burst Length (BL) 2 and 4 (1) SSTL_2 Interface Products (TC59LM913AMG, TC59LM905AMG) Speed version -50 -55 -60 Clock Cycle Time (minimum) CL=4 5.0ns 5.5ns 6.0ns Clock Frequency (maximum) CL=4 200MHz 182MHz 167MHz Data Transfer Rate (maximum) CL=4 400Mbps 363Mbps 333Mbps Random Read/Write Cycle Time (minimum) 25.0ns 27.5ns 30.0ns Random Access Time (maximum) 22.0ns 24.0ns 26.0ns Operating current (maximum) 240mA 225mA 210mA At Single bank operation Powerdown current (maximum) 80mA 75mA 70mA Self-refresh current (maximum) 20mA (2) SSTL_18, HSTL Interface Products (TC59LM914AMG, TC59LM906AMG ) Speed version -37 -45 -50 Clock Cycle Time (minimum) CL=5 3.75ns 4.5ns 5.0ns Clock Frequency (maximum) CL=5 266MHz 222MHz 200MHz Data Transfer Rate (maximum) CL=5 533Mbps 444Mbps 400Mbps Random Read/Write Cycle Time 22.5ns 25.0ns 27.5ns (minimum) Random Access Time (maximum) 22.0ns 22.0ns 24.0ns Operating current (maximum) 280mA 260mA 240mA At Single bank operation Powerdown current (maximum) 90mA 85mA 80mA Self-refresh current (maximum) 20mA Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, and displays for the computing, wireless, networking, automotive and digital consumer markets. TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the third largest semiconductor company worldwide in terms of global sales for the year 2002 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com. (1) When used herein, megabit and Mb means 1024x1024 = 1,048,576 bits using powers of 2.