INDUSTRY

System and application development for HPRC (High Performance Reconfigurable Computers) and ASCM (Application Specific Computing Machines) is decidedly not easy. The Bloomington, IN based startup, MNB Technologies, Inc., offers its clients a full range of services from system architecture (including hardware design) to applications development, intended to take much of the pain out of deploying HPRC and ASCM solutions. Nick Granny, MNB’s VP & Operations Director said, “Much of the promise of reconfigurable computing has gone unfulfilled because its practitioners overstated its capabilities and understated its complexity. This resulted in some clever hardware but terrible use models.” MNB’s approach is to integrate the SPMD use model (C++, MPI, OpenMP) with both commercially available and custom designed hardware platforms such that application developers may work in a familiar environment while the hardware acceleration is done with MNB supplied models and API’s. “It’s unrealistic to expect application developers having a long familiarity with traditional parallel computing use models to abandon them in favor of a wildly different paradigm any time soon. It is equally unrealistic to expect the reconfigurable computing industry to remove the hardware engineer from the application development process any time soon.” (Bob Cruise, MNB’s Computational Sciences Director). MNB minimizes these two problem areas by providing the HPC application developer with the bridge to the hardware-based accelerator. Another area that has historically been problematic is integration of floating-point arithmetic in FPGA based accelerators. MNB Technologies has a library of hardware optimized floating-point functions that allow the accelerated algorithm to enjoy pipelined and parallel execution without resorting to the “discomfort” of fixed-point arithmetic. On the custom hardware side of HPRC and ASCM, recent mainstream availability of feature-rich FPGA’s (e.g. the Xilinx Virtex-II PRO-X) and new 4GB memory modules are making “1 byte per FLOP” memory a reality. Today it is not unreasonable for us to package 8TB of high speed SDRAM along with 768M gates of 100MHz reconfigurable logic and a pair of server class hosts in a single 32U chassis. The result is a distributed memory machine with a “virtual shared memory” that can allow great flexibility in use models. “Clusters of this class of machine will be HPRC’s bridge to Petaflop performance in the very near future; scale the machine down somewhat and you can have an affordable ASCM the size of a pizza box that delivers 500GB of memory and 500GFLOPS of acceleration. It’s our mission to help our clients realize this level of computational performance” said MNB”s president, Martina Brisudova.