INDUSTRY

During a talk at the Microprocessor Forum in San Jose, IBM's Power5 Chief Scientist Balaram Sinharoy said the new chip is intended to build upon the Power4 design with enhancements made to improve performance, allow more processors to be used in a system and to improve power efficiency. At the same time, Sinharoy said that all code developed for the Power4 will be fully compatible with the Power5. Like the Power4, the Power5 contains two processor cores on one chip. These cores share one 1.92 MB on-die L2 cache compared with a 1.44MB L2 on-die cache on the Power4. The Power4 and Power5 both have an off-chip L3 cache, but IBM designed the L3 cache to connect directly to the L2 cache instead of between the memory controller and the processor like on the Power4. Sinharoy said that this "backdoor" cache allows the Power5 to be more scalable with multiprocessor designs. The "backdoor" cache improves performance by reducing the L3 cache latency. The Power5 also incorporates an on-die memory controller to improve performance and reliability. Each Power5 can support up to 1024GB of memory, compared with 512GB for each Power4. Since the memory controller is on the chip, designers need only to attach memory to the chip instead of going through a northbridge. IBM will distribute the Power5 in a Multi-chip Module that is a 95mm by 95mm block of four Power5 chips with four 36MB off-chip L3 caches. Up to 16 of these Multi-chip Modules can be implemented together for a total of 128 logical processors. The arithmetic of that is two cores per Power5 processor, four processors per module and 16 modules. Sinharoy said that all that needs to be added to a Multi-chip Module to create a system was any I/O required and memory. The Power4 collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle. The Power5 doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle. Sinharoy said that is was not uncommon to see a "40 percent improvement for SMT (Symmetric Multithreading) instructions," a key performance characteristic for server processors, over the Power4. IBM also added a power management scheme to the Power5 that Sinharoy claims will drastically reduce power consumption and heat generation. His presentation contained no information on the power needs or heat dissipation characteristics of the Power5. The new chip is scheduled to launch in mid-2004. IBM plans to release the Power5 chip in a 64-processor server code-named Squadron. Power5+, which will be similar to the Power5 but manufactured using a 90-nanometer process, is tentatively scheduled for 2005. Finally, Sinharoy said that a Power6 is "well underway" and scheduled for introduction in 2006.