INDUSTRY

HSINCHU, TAIWAN -- Taiwan Semiconductor Manufacturing Company (TSMC) has successfully produced the foundry industry's first fully functional four-megabit (4Mb) SRAM chips using its next-generation 90-nanometer logic technology. The test devices have undergone extensive testing and verification to confirm their functionality and reliability. This milestone makes TSMC the first foundry company to deliver a functional test device using the semiconductor industry's most advanced process technology, more than one year ahead of the recently announced ITRS Roadmap for delivery at this node. The 4Mb SRAM devices feature a 65-nanometer gate length and the world's smallest 6T SRAM cell, measuring less than 1.3 square microns. That is nearly one-half the size of same device on 0.13-micron process technology. The devices feature an interconnect technology including both dual-damascene copper and low-k dielectrics. TSMC expects to enter pilot production of its 90-nanometer process by the fourth quarter of this year. Volume production of the 90-nanometer process will commence almost entirely on 300mm wafers. "Since we introduced our 0.13-micron process in 2000, TSMC has surged ahead of the ITRS roadmap for new process development. With this achievement, we maintain our position ahead of that roadmap," said Dr. F.C. Tseng, Deputy CEO of TSMC. "The true essence of the foundry industry is to provide our customers with the technology they need to develop innovative new products," said Rick Tsai, president of TSMC. "Industry-leading technology developments such as this guarantee our customers' competitive advantages." TSMC announced the basic modules for a 90-nanometer CMOS logic process in April of 2001. The technology is fully compliant with anticipated 90-nanometer targets and is supported by TSMC's partners and key customers. The company expects to deliver the industry's most complete 90-nanometer process portfolio, including high-performance, low-power, mixed-signal/RF, and embedded memory options. "TSMC is, and always has been, committed to developing its own process technology. However, the decision to embark upon a new technology is never made alone," said Dr. S.Y. Chiang, Senior VP of R&D at TSMC. "It requires significant collaboration to ensure that our efforts are aligned with designers' needs." To satisfy diverse requirements, the process will be made more portable and therefore improve time-to-market. TSMC provides partners with 90-nanometer IC design rules, transistor models, and interconnect parameters. A number of leading IP, library and EDA tool companies have already announced their intention to design first with TSMC's 90-nanometer process. This alignment should increase the speed in ramping the 90-nanometer process. For more information visit www.tsmc.com