INTERCONNECTS

Triples performance to 5.2 GT/s, enhances flexibility and power management: Further advancing the performance and capabilities of high-performance systems and subsystems, the HyperTransport Technology Consortium today announced it has released its new HTX3 specification, a major enhancement to its HTX expansion connector specification. The HTX Connector specification defines the electrical and mechanical characteristics of an EATX motherboard interface connector, enabling CPUs to connect directly via a HyperTransport link to add-in card subsystems requiring HyperTransport’s state-of-the-art low latency and bandwidth. The EATX motherboard is a popular architecture used in high-performance workstations, servers, embedded systems and storage systems. “Continued enhancement to the popular HTX specification reflects the Consortium’s commitment to lead in the support of compute-intensive applications and system development,” said Mario Cavalli, general manager of the HyperTransport Technology Consortium. “Applications such as financial processing, real-time data analysis and HPC server clustering continue to drive the need for higher performance solutions and will be enhanced by the low latency and performance headroom delivered by HTX designs. The HTX3 specification embodies the on-going learning that the Consortium continues to gather from its large membership and extended product ecosystem.” New HTX3 solutions will benefit from the increased performance, flexibility and power management capabilities enabled by the new specification. In addition, backward compatibility preserves the value of existing HTX solutions. HTX3 supports up to 5.2 gigatransfers per second bandwidth (2.6 GHz clock rate), which more than triples the 1.6 gigatransfers per second bandwidth of the previous HTX specification (800 MHz). Moreover, support for link splitting enables designers to implement either one x16 link, one x8 link or two x8 links on a single connector. The ability to split one HyperTransport link into two allows the HTX subsystem to be connected to separate CPUs for better clustering performance and RAS support, a capability that is increasingly required by high-performance subsystems operating in multiprocessor designs. HTX3 also includes support for more sophisticated power management. Users can now leverage a signal pair to enable and disable link activity during power management state transitions. The specification also offers dynamic, auto-sensing, hardware-based, self-configuring power management capabilities that give end products the intelligence to best optimize the power consumption of HyperTransport components. As a result, the HTX3 specification enables designers to take full advantage of a broad range of power management states for maximum energy savings. With a rising number of HyperTransport-based field-programmable gate array (FPGA) solutions under its belt and with FPGAs representing the majority of controllers and processors utilized in HTX subsystem products, the HTX3 specification includes a section dedicated to detailed FPGA design considerations and guidelines. “Our recently announced Stratix IV family of FPGAs was designed from the start to support HT3.0 and will enable strong performance for HTX3 board designs,” said Dr. Misha Burich, Altera’s senior vice president of research and development.