OIL & GAS

SAN JOSE, Calif., Microprocessor Forum -- Sun Microsystems, Inc. today kicked-off the 16th annual Microprocessor Forum by disclosing additional information on its Throughput Computing strategy and the new UltraSPARC IV processor. The UltraSPARC(r) IV has the potential to double the throughput of Sun's existing high-end and mid-range systems when it hits the market in the first half of 2004. In a recent Microprocessor Report article on Throughput Computing, In-Stat/MDR senior analyst Kevin Krewell wrote: "We're excited to see Sun taking aggressive steps to reinvent and redefine server processor performance and challenge the industry with this daring move. With a renewed sense of excitement and challenge (...), Sun is once again taking up the role of innovator and is showing it will not allow Intel's Itanium juggernaut to roll over it." Throughput Computing is core to Sun's strategy for the future of Network Computing and its SPARC(r) and Solaris(tm) systems. At the heart of this new strategy is Chip Multithreading (CMT), a design concept that allows the processor to execute tens of threads simultaneously, thus enabling tremendous increases in application throughput. Sun is bringing CMT to the market in a phased approach. First generation CMT processors, such as the UltraSPARC IV family of processors, can enhance current UltraSPARC III system throughput, initially by up to 2 times, and later by up to 3 to 4 times the current levels. In the future, Sun will be rolling out a more radical CMT design, which will first appear in Sun's blade platform in 2006, that can increase the throughput of today's UltraSPARC IIIi systems by up to 15 times. The UltraSPARC IV processor will introduce CMT technology into Sun's current mid-range and high-end server lines. This new fourth generation UltraSPARC processor maintains Sun's tradition of binary compatibility, preserving the investment customers have made in development tools and application software, and it will also help current Uniboard-based Sun Fire(TM) customers preserve the investments made in their systems. The dual-threaded architecture of the initial member of the UltraSPARC IV processor family consists of two UltraSPARC III cores and includes on-chip tags for 8 MBs of off-chip 2-way set-associative Level 2 cache per core. A dynamic arbitration scheme allows each thread to make optimal use of the available L2 bandwidth. Other shared interfaces on the UltraSPARC IV processor include an on-chip memory controller supporting up to 16 GBs of DRAM, and a system interface unit providing access to the Sun(TM) Fireplane interconnect fabric. Built with Texas Instrument's 130 nanometer (nm) process technology, the processor will operate at an initial frequency of 1200 MHz, moving higher over time. The performance improvements from the UltraSPARC IV design are expected to range from 1.6 to 2.0 times the throughput of today's 1200 MHz UltraSPARC III processor on typical business applications. Customers' performance will vary based on system configuration and the nature of the workloads. A future member of the UltraSPARC IV family will take advantage of Texas Instrument's 90nm technology node to provide a number of architectural enhancements and increase clock speeds, in order to increase throughput by up to 3 to 4 times today's UltraSPARC III.