PROCESSORS

SAN JOSE, CA -- The Nios(TM) embedded processor, the programmable logic industry's first soft processor core, will be enhanced for high-bandwidth applications such as networking, telecommunications, and mass storage, Altera Corporation (Nasdaq:ALTR) announced today. Version 2.0 of the Nios embedded processor will include features such as customizable instruction sets and simultaneous support of multiple bus masters with arbitration for optimizing overall system performance. The Altera Nios soft core, a general-purpose RISC CPU provided as part of Altera's Excalibur(TM) embedded processor solutions, enables engineers to easily integrate peripherals and implement entire systems onto a single programmable logic device (PLD). The Nios embedded processor was designed specifically for Altera PLDs to support all lookup table-based device families from the high-density, high-performance APEX(TM) II, Mercury(TM), APEX, and Excalibur ARM(R)-based device families to the low cost ACEX(TM) devices. After selling more than 2,500 Nios embedded processor development kits since its introduction in June 2000, Altera is unveiling the Nios 2.0 soft processor to give embedded designers increased system performance and configurability. New features will include instructions that can be customized as hardware extensions to the Nios instruction set, a feature that up until now can only be found in high-performance, configurable embedded processors targeted at ASIC designs. "We have found the Nios processor to be a powerful, reliable platform for developing and implementing complex algorithms," said Santo Maggio, project leader at Alcatel's Optical Multi-Service Node (OMSN) Lab. "The combination of microprocessor functionality and programmable logic allows designers to explore the optimum implementation of digital functions." The Nios 2.0 processor's new custom instruction capability and simultaneous multi-master bus architecture will deliver Gigabit speeds to bring a level of configurability and optimized system performance never possible before in a soft core embedded processor for PLDs. "Customers are demanding better ways to handle multiple data streams in their systems. The optimizations in the Nios 2.0 processor enable the core to be even more widely adopted in embedded applications requiring high system throughput and performance," said Jordan Plofsky, Altera's senior vice president of vertical markets and embedded processor products. Optimized for size and speed, the Nios 2.0 embedded processor is capable of more than 80 MHz clock frequency and can be implemented using as few as 900 logic elements (LEs) in Altera PLDs. Complete Nios systems can include a wide range of peripherals, memory, and external interfaces allowing developers to create a processor tailored to their specific application. For example, a peripheral-rich 32-bit Nios system design, which includes a UART, timer, 4 PIOs, hardware multiplier, and external SRAM and Flash interface, uses only 3000 LEs and consumes only 12 percent of an APEX II 2A25 device. A 16-bit minimal Nios system, including a memory interface, UART, and PIO would use 1200 LEs, and consume only 25 percent of Altera's mid-range density ACEX 1K100 device. These and other peripherals are provided as part of the Excalibur development kit, featuring the Nios embedded processor. The Nios 2.0 embedded processor will also include an on-chip debug (OCD) peripheral that accelerates the software development process, and supports real-time debugging of software applications such as those typically found in network and telecommunication systems. The Nios embedded processor OCD peripheral supports hardware (data) break points and real time software trace to a large external buffer. "By using the Nios processor, we reduced our development time, shortened our time-to-market and improve our capability to update our product in the field," said Paolo Taina, group leader at Alcatel's OMSN Lab. "As a result, most of our future programmable logic designs include the Nios processor, and we eagerly anticipate the expanded functionality in Nios 2.0." For more information visit www.altera.com