PROCESSORS

ST. LOUIS, MO -- Erlang Technology Inc., a fabless semiconductor company that designs, develops and delivers leading-edge switch fabric components, and NEC Corporation (NEC) (NASDAQ: NIPNY), through its U.S. subsidiary NEC Electronics Inc., today announced the launch of their revolutionary switch-fabric architecture and first Erlang Network Element Technology (ENET) product, the Se chipset. The architecture, developed at Erlang by a key team of industry-seasoned communication and semiconductor engineers and scientists formerly of Washington University's Research Group in Telecommunications (RgiT), will have several patented technologies that make this family of switch fabrics truly leading edge. Erlang's architecture is protocol-independent, linearly scalable, has distributed control, and is terabit-capable. The switch-fabric chipset will be implemented in NEC's ASIC process technology and offered solely through NEC Electronics' extensive North American sales and support channels. The first chipset, with two components, SeC (Core fabric) and SeI (Interposer), allows for ease of system integration with switching capacity from 10 to 40 gigabits/second. Erlang prides itself on solving the switch-fabric problem with advanced algorithm development at both the chip and system level instead of relying on a brute force approach that results in high-speed, high-power devices that are difficult to integrate into a system. The Se's application of these algorithms results in lower-speed, lower-power and lower-cost devices, enabling cutting-edge, mid-range and high-end systems that enable integrators to meet the high-performance requirements of today's intranets and the Internet. Erlang's ENET family includes some patented technology that makes the switch fabric unique and truly scalable. -- Patent-pending, multichannel switching (MCS) technology will enable increased port rates by grouping multiple ports to form higher rate links, while at the same time keeping total capacity constant. Se therefore will be able to aggregate multiple ports to form a higher-speed bit pipe. On a practical level, Se will solve common scaling problems. With MCS, scaling to higher line rates while protecting the hardware investment in the switch fabric and associated systems designs will be very possible. For Se, four OC-12 ports can be configured as an OC-48 port. MCS also enables parallel processing without complicated re-sequencing of packets or cells. This feature increases the scalability of Se. -- Distributed control and scheduling is an architectural advancement, first implemented in the Se, that will do away with the need for a centralized scheduler ASIC required for many common switch-fabric architectures. This advancement enables linear, highly scalable fabrics, reduces the cost of the entire chipset, reduces the complexity of system design and development effort, and decreases time to market. -- The Se chipset uses the concept of an interposer chip that provides a glueless interface to network processor units (NPUs). The same architecture will apply to Erlang's next-generation chipset, the 80-640 gigabits/second Xe, which is due out in early 2002 for carrier equipment vendors. -- The Se Interposer supports Agere Payload Plus and APC chipsets seamlessly, which means no additional glue logic is needed. Erlang has developed system solutions for the integration of the Se switch fabric with most leading-edge third-party network processors. -- The Se chipset is available as standard silicon today to new emerging applications, like multi-services ATM / IP / MPLS switching routers, TDM switching for optical cross-connects, server farm load distribution, virtual private networks, content delivery networks, fiber-channel applications. -- Providing the next migration path in the ENET architecture, the Xe switch fabric will be scalable up to 640 gigabits/second and will support 256 OC-48c, 64 OC-192c and 16 OC-768c channels. As with the Se switch fabric, the Xe will also be protocol-independent, linearly scaleable, have distributed control and include other patented technology such as Train-processing Train-queuing (TpTq) to enable terabit scalability and reduce power dissipation by lowering clock rates to manageable levels. -- The Xe chipset will also include NEC's advanced, high-speed SerDes technology, making the design of high-speed backplane interfacing simpler and providing higher reliability of data transfers and reduced systems cost. The switch fabric will be targeted toward enterprise and carrier- class OEMs designing products such as multi-service switches and routers, metropolitan optical network equipment, IP service platforms and edge access equipment. "Notwithstanding the industry downturn, we've focused on developing high-performance, highly scalable switch fabric that system vendors are demanding for their products," said Erlang Chairman, President and CEO Greg Miller. "With the new Se chipset, we've done just that. We are very proud of how far we've come as a company." "The partnership with Erlang Technology will expand NEC Electronics' networking product offerings," said Dr. H. Yoshizawa, vice president of NEC Electronics' Communications Strategic Business Unit. "By implementing Erlang's innovative switch-fabric technology in our ASIC process, NEC customers will be able to design high-performance products featuring components manufactured by a world-class, highly dependable semiconductor vendor." The Se chipset is implemented in NEC's well-established CB-11 0.18-micron ASIC technology. Both the SeI and SeC chips are housed in 696-pin tape BGA packaging. For more information visit www.erlangtech.com or www.nec.com