SCIENCE

Intilop announced broadening of their 10G bit TOE series of IPs and solutions by offering an integrated 1G bit EMAC as an option, instead of 10G bit EMAC. They also delivered these Mega_IP_SoC cores for Xilinx and Altear FPGAs that integrate their much heralded flagship 10G bit TCP Offload Engine, their own very low latency 10G EMAC, CPU interface, mdio controller. The performance and latency of their TCP Offload engine has been validated by many customers and has been proven to increase TCP performance by 10 – 20 times in a typical networking system. It also extends the TOE’s capability of providing up to 128 and more concurrent TCP sessions, depending upon FPGA size. They accomplished this feat without compromising highest throughput and ultra low latency in the industry. The latency of ~100 ns was made possible by patent pending advanced dynamic array search architecture.
Optional features in TOE_SoC are; a variety of CPU interfaces, PCIe Gen-2/3. This 10G TOE implements Full TCP Offload and reduces CPU’s involvement in TCP processing by about 95%. It presents a very attractive solution to the latency sensitive financial markets and is a critical building block for the current and future high performance networking equipment in converged IP networks. It is targeted towards Xilinx Vertex-6 and Altera GXIII/IV/V FPGA families and can also be targeted to other FPGA families. Further details are available upon request.
Due to its flexible architecture, the developers of high end FPGAs/ASICs/ASSPs, Network adapters, Lan-on-Mother board (LOM) and very large scale FPGA-SoC IP integrators can provide differentiated solutions to the end users in financial markets, web servers, email servers, high end servers in Data centers, Government network systems, university network systems. The 10G TOE is intilop’s 3rd generation flagship TOE architecture, based upon their industry-proven 1 G TOE architecture. The highly flexible and scalable architecture offers customers, ability to customize it to suite their specific application. This is the only TCP offload engine that is also scalable and is easily customizable to suit different types of network traffic.
The highly integrated, highly scalable full Offload TOE employs patent pending high performance VLIW microcode machines and advanced search hardware design techniques that test the limits in FPGA and ASIC design/integration technologies. It employs best of cut-through and store-and-forward architectural features that utilize intilop’s third generation TOE, EMAC and DMA designs. There are so many features that are easily configurable which make the value proposition even more powerful. The unprecedented customizable features as options include; scalable number of TCP sessions, multiple (2-4) 10G Ethernet MACs, VLAN support, TCP Bypass mode, Fiber Channel over Ethernet (FCoE) support and others.

"We responded to our customer’s requests to deliver a series of TOE engines with least latency and highest bandwidth possible that are also customizable. Having a fixed architecture does not provide the capability to deliver differentiated solutions. We hope that with this type of scalability, flexibility and performance, Intilop’s 10G TOE really opens up tremendous opportunities for next generation of hyper performance advanced system solutions in IP networks”, said K Masood, President and CTO.