SCIENCE

SAN JOSE, CA -- Cypress Semiconductor (NYSE:CY) today announced the availability of the world's largest Complex Programmable Logic Device (CPLD), the Delta39K200, which includes 200,000 gates with 3,072 macrocells and 480 Kb of embedded communications memory. The Delta39K200 CPLD provides double the logic capacity and memory of the previous largest CPLD in the world, the Delta39K100, also from Cypress. The Delta39K(TM) family -- which spans seven device densities, ranging from 30,000 to 350,000 gates -- is the first CPLD to embed high performance communications memory and offers more memory than any FPGA. "Delta39K CPLDs exemplify the breadth of Cypress's engineering capabilities and intellectual property, and deliver the high speed, predictable timing and ease-of-use advantages of a CPLD at FPGA densities. All these capabilities, combined with advanced clock management features, put these CPLDs in the heart of the backplane datapath," said Geoff Charubin, director of marketing for Cypress's data communications division. "Programmable high speed I/Os, which support a plethora of I/O standards, now enable interoperability among the physical layer devices, network processor and Network Search Engine (NSE) at wire speed." "With the Delta39K, Cypress has redefined the term CPLD," said Rajiv Nema, marketing manager of programmable products at Cypress. "These system-on-a-chip devices provide an ideal solution to the designers of router, basestation and storage network linecards. Their high speeds, combined with embedded communications memory, enable efficient implementation of data manipulation functions like packet processing, encoding/decoding and forward error correction." The Delta39K architecture consists of logic block clusters (LBCs), each of which has 128 macrocells -- eight 16-cell macrocell logic blocks -- connected by a Programmable Interconnect Matrix(TM) (PIM(TM)). Each LBC has 16 Kbits of single-port SRAM cluster memory, configurable as synchronous or asynchronous and as x1, x2, x4, or x8. The cluster memory can be cascaded with other cluster memory blocks to implement wider and deeper memory functions. In addition to cluster memory blocks, each LBC has an associated channel memory block. The 4 Kbit channel memory uses Cypress' true-dual-ported cell to offer optimized dual-port and FIFO memory with completely independent write and read clocks. Each channel memory block includes FIFO control and the dual-port arbitration logic needed to implement extremely fast and powerful specialty memory functions. The Delta39K device offers FIFO performance as high as 200 MHz. The channel memory, like the cluster memory, is configurable as x1, x2, x4, or x8 and its width and depth can be expanded. The LBCs and channel blocks communicate through abundant vertical and horizontal routing channels. These channels also connect to a block of I/O pins at each end to provide maximum pinout flexibility and true In-System Reprogrammability(TM) (ISR(TM)). ISR gives designers the flexibility to change a design with the confidence that speed and pinout will not be altered. Delta39K CPLDs are offered with a pin-to-pin propagation delay as low as 7 ns and true in-system performance in excess of 233 MHz. The devices are manufactured using a 0.18 micron, six-layer metal process, the most aggressive process ever used for a CPLD. Innovative package options include an embedded non-volatile Flash memory die with the Delta39K die, creating a unique non-volatile solution and eliminating the need for an external boot PROM. Each device in the Delta39K family includes a programmable, Spread Aware(TM) phase locked loop (PLL) -- with unmatched multiply, divide and clock edge control options -- that provides four global clocks to all logic clusters, memories and I/O cells to maintain precise on- and off-chip timing. The Delta39K family of CPLDs are fully supported by Cypress's Warp(TM) Release 6.1 design tool suite. Warp is a fully integrated programmable logic design environment that accepts VHDL, Verilog, Finite State Machine, and Schematic Entry as design input mechanisms. Warp also performs synthesis and fitting in a single step to speed the design process. In addition, Warp features an Architecture Explorer(TM) and Static Timing Analyzer to quickly pinpoint design fitting and critical path timing to aid in fast debugging and timing closure of logic designs. Warp also includes a fully capable simulation tool for design verification. All of the advanced features mentioned above make designing for the Delta39K family, the largest CPLDs in the world, simple and efficient. For additional information visit www.cypress.com