SCIENCE

Magma Design Automation and Icera have announced joint development of Icera's 28-nanometer (nm) high-performance, low-power system-on-chip (SoC) design flow for its next-generation chipsets. Icera devices are used by OEMs globally to deliver extremely small, fully software-based multimode 4G LTE/3G/2G cellular modems for smartphones, and mobile broadband devices such as USB sticks, tablets and netbooks. Icera chose Magma's Talus platform because it provides a highly integrated flow that enables Icera to address 28-nm design complexity, improve area efficiency and reduce power consumption while accelerating turnaround time.

"To maintain technical leadership in the cellular modem business, Icera cannot afford to compromise on performance, power consumption or area efficiency," said Peter Hughes, vice president of Silicon Engineering and Operations at Icera. "The advanced technology and tight integration of the Talus platform enable Icera to meet our stringent power and area targets and to reduce time to market for our next-generation 28-nm soft modem chipset."

"The recent enhancements to the Talus platform were developed specifically to address increasing design complexity at the 28-nm node while improving designer productivity dramatically," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "Offering the capacity to process 1 million cells per day, integrating the Tekton-based MX timing engine to ensure correlation and accelerate timing closure, and supporting advanced low-power design techniques, Talus is the clear path to 28-nm and smaller SoCs."

Talus 1.2 Increases Implementation Throughput, Decreases Power for Icera Chipsets

Talus 1.2's new advanced on-chip variation (AOCV) driven optimization significantly reduces pessimistic design margins that are required in traditional flows, and Icera plans to leverage this capability to improve the performance of its soft modem chipsets. Unlike other approaches, this optimization is performed throughout the Talus flow, providing convergent and robust timing while at the same time reducing any area penalty related to OCV effects. With Talus 1.2 designers can improve silicon correlation and minimize power consumption.

Talus 1.2's advanced clock gating techniques help customers significantly reduce both area and power, particularly in the clock network. This allows the core processing functions to achieve required operating frequencies while remaining within a tight power budget.

In addition, Talus 1.2 offers tight timing correlation throughout the flow and timing sign-off through its new MX timing engine derived from Tekton, Magma's extremely fast and accurate standalone static timing analyzer. With reliable timing numbers that Talus delivers early in the design process, designers can make better design decisions throughout the flow and have confidence in achieving timing convergence faster.