SCIENCE

PORTLAND, OR -- The PCI-SIG, the Special Interest Group responsible for PCI, PCI-X and PCI Express industry-standard I/O technologies, announced today that its board of directors has approved the official public release of the PCI Express specifications. PCI Express is a new serial I/O technology compatible with the current PCI software environment that offers low-cost, scalable performance for the next generation of computing and communications platforms. The documents being released include the Base specification that covers the electrical, protocol and software aspects of the technology as well as the Card specification for design of PCI Express cards and slots in computing and communications platforms. Together, these two specifications provide all of the information that silicon and systems engineers need to begin their PCI Express product designs today. PCI Express Addresses Current and Future I/O Needs "PCI Express was developed with the common goal of extending PCI to meet the present and future computing and communications interconnect requirements of our members," said Tony Pierce, chairman of the PCI-SIG. "With significant developer interest, PCI Express enters the enablement phase." "PCI Express provides the performance and system design flexibility required for the next generation computing and communications platform component interconnects while also providing a long-term path to improved I/O slots," said Al Yanes, president of the PCI-SIG. "Moving forward, PCI Express will hold a prime spot at our PCI-SIG Compliance and Interoperability Workshops, Plugfests and Developers Conferences." "The PCI Express Base and Card specifications establish a solid foundation by balancing cost, performance, compatibility and advanced features necessary for both computing and communications platforms," said Ajay Bhatt, chairman of the PCI-SIG's PCI Express workgroup. "Building on excellent collaboration and outstanding technical contributions from its members, the PCI Express workgroup continues to work diligently on enablement efforts for early silicon and system designs while developing additional PCI Express specifications to support new applications and form factors." Bandwidth, Scalability and More Suitable for both chip-to-chip and add-in card implementations, PCI Express defines a packetized protocol and a layered architecture that enables attachment to copper, optical, or emerging physical signaling media. These properties, combined with an initial bit rate of 2.5 Gigabits per second per lane per direction, make PCI Express an ideal attach point for performance-intensive applications such as next-generation graphics, video editing and streaming multi-media, as well as high-speed interconnects such as 1394b, USB 2.0, InfiniBand and Gigabit Ethernet. In addition to offering superior bandwidth, performance and scalability in both width and frequency, PCI Express offers other advanced features built from the ground up. These features include QoS (quality of service), aggressive power management, native hot-plug, bandwidth per pin efficiency, error reporting, recovery and correction and innovative form factors, and meet the growing demands for sophisticated capabilities such as peer-to-peer transfers and dynamic reconfiguration. PCI Express also enables low-cost design of products via low pin counts and wires. The PCI Express architecture unifies general-purpose I/O and graphics I/O and provides many RAS breakthrough features to enable robust system designs that combine improved partitioning, superior performance and low-cost implementation. The inherent nature of PCI Express will enable exciting new form factors beyond its current PCI-compatible form factor, as well as interoperability options for innovative system designs. A linearly scaled 16-lane PCI Express interconnect can provide data transfer rates of more than 8 Gigabytes per second.