SCIENCE

Centec Networks says that it has expanded its family of packet-processing chipsets with the CTC6048. The second-generation IP/Ethernet switching processor integrates a Layer 2 through Layer 4 packet-processing engine, traffic manager, and fabric interface.

Centec Networks says its CTC6048 processor combines compact size and 100-Gbps performance in support of next-generation Carrier Ethernet and packet transport networks. The CTC6048 is designed for fixed and modular systems used in access, edge, and aggregation IP/Ethernet routing switches, packet transport network (PTN) platforms, optical line termination (OLT) systems, and wireless backhaul gateways.

Integrated memory reduces system cost, and the device performs true consistent distributed processing for both unicast and multicast packets, Centec asserts. The CTC6048 incorporates a variety of advanced features for implementing carrier-class transport, including:

• On-chip Ethernet operation, administration, and management (OAM) based on IEEE 802.1ag and ITU-T Y.1731
• <50-ms automatic protection switching (APS) based on ITU-T G.8031/8032
• Synchronous Ethernet and packet timing protocols such as IEEE 1588v2, Network Time Protocol (NTPv4)
• Multiprotocol Label Switching–Transport Profile (MPLS-TP) and Provider Backbone Bridge Traffic Engineering (PBB/PBB-TE) technology.

Additionally, patented loopback mechanisms ensure NPU-like packet-processing flexibility, and multiplexing/demultiplexing technology enables the ability to scale to 256 full-service network ports per chip, according to Centec. Scalability is further improved through the use of configurable internal and external table sizes and the built-in fabric interface to connect to Centec’s CTC8032 switch fabric in a distributed chassis system with total capacity of 5.12 Tbps. A single device can be configured into different form factors such as 48x1GE+4x10GE, 8x10GE, 48x2.5G to further reduce inventory management cost.

Centec’s CTC6048 processor supports a combination of hardware-based IPv4 and IPv6 dual-stack routing, MPLS switching, and various types of advanced multicast and IP/MPLS tunneling protocols including IPv4, IPv6, Generating Routing Encapsulation (GRE), User Datagram Protocol (UDP), MPLS and Provider Backbone Transport (PBT). Also included is support for L2/L3 Virtual Private Networks (VPNs) and native high-performance multicast.

The CTC6048 device also supports service-based Access Control List (ACL), plus full, Hierarchy Quality of Service (H-QoS) policing and queuing/scheduling/shaping, built-in OAM and accounting, and carrier-class reliability using APS, fast convergence, and CPU protection. Bandwidth provisioning functions are supported through the use of an advanced flow classifier and a flexible 80-Gbps fabric interface. Capabilities are further extended through the use of optional interfaces to external memory.

The CTC6048 packet processor is sampling now, with volume production scheduled for the first quarter of 2011. The device is packaged in a 1520-pin Flip Chip-Ball Grid Array (PBGA) and priced at $250 in 10,000-piece quantities.

A reference design also is available, including a 1U box with 48 Gigabit Ethernet ports, or the equivalent of 32 1000Base-T ports and 16 Small Form Factor Pluggable (SFP) ports, plus eight 10 Gigabit Small Form Factor Pluggable (XFP) ports. Also included is built-in 20-Mbit Ternary Content Addressable Memory (TCAM) and 18-Mbit static random access memory (SRAM) for table expansion. The box can be also used as a line card in the chassis system with a specially built backplane.