SYSTEMS

SAN JOSE, CA -- Plato Design Systems, Inc., an Electronic Design Automation (EDA) company that provides next generation, scalable routing solutions for Systems On Chip (SoC) designs today announced a world record for routing a 2 million-gate flat design, using Plato's NanoRoute on the Sun Microsystems, Inc. Sun Fire(TM) 4800 Midframe server. The results represent an over 20-fold shorter turnaround time over other physical design solutions available to chip designers. Routing was done in 11 minutes and 30 seconds, with Plato's NanoRoute running on a 12-CPU Sun Fire 4800 server. In addition, the combination of NanoRoute's scalable routing algorithm and Sun's scalable hardware enables designers to handle 10X the size of their current designs for their next and future generation products. "This showcases the unprecedented performance and scalability of our router, NanoRoute, and demonstrates the powerful combination of our scalable routing solution and the Sun servers," said Dr. Limin He, president and CEO of Plato. "This type of performance is critical for semiconductor companies seeking physical design solutions that address the increasing challenges of design complexity and time-to-market." The 2 million-gate chip is a real design that was taped out by a fabless semiconductor company. Plato also tested a number of additional designs that demonstrated similar performance. Based on the industry's first graph-based(TM) routing technology, NanoRoute performs parallel routing on multi-CPU workstations. In benchmarking the 2 million-gate design, NanoRoute demonstrated run-time speed-up and capacity increases that were linear to the number of CPUs. This world record obtained with the 12-CPU Sun Fire 4800 server eclipses one existing router's performance by 20 times and beats another existing router by 30 times. Test results on other designs, ranging from 1.5 million-gates to 3-million gates, showed 10 to 20 times runtime improvements. By cutting routing time from days to minutes, NanoRoute plays a key role in shortening design cycle time and time-to-market. For more information visit www.platodesign.com.