VISUALIZATION

The Workshop on Massively Parallel Processing is a forum for the discussion of parallel processing involving hundreds to thousands of processors. Topics range from novel architectures to algorithms to applications. The Fourth Workshop on Massively Parallel Processing (WMPP'04) builds on the success of the three previous successful workshops, held as part of IPDPS'01, IPDPS'02 and IPDPS'03, respectively. WMPP has picked up momentum and is now pushing the limits of single day format. Technical presentations have come from industry (e.g. IBM), from national laboratories (e.g. UCAR, JPL), and from academic institutions from across the globe. The First and Second workshops featured invited keynote talks by Peter Kogge of Notre Dame and David Bader of the University of New Mexico, respectively. The Third workshop featured an invited keynote talk by Thomas Sterling of Cal Tech and NASA JPL. Following the usual practice at IPDPS, all WMPP papers have been published with the paper abstracts in a hardcopy volume and the complete paper in an accompanying CD-ROM. WMPP'04 is soliciting papers for general sessions as well as two special sessions on massive parallelism for solving grand challenge problems and on massive parallelism using FPGAs for architectural research. The invited keynote talk for the Fourth workshop will be Mootaz Elnozahy, Senior Manager and Master Inventor at IBM Research in Austin Texas. General Sessions WMPP'04 is now soliciting papers for the general sessions. Manuscripts containing original unpublished research are solicited in all areas of massively parallel processing. Topics of interest include, but are not limited to, the following: Algorithms and models for massively parallel computation SIMD and MIMD massively parallel systems case studies Teraflop and petaflop system development and application experience Intelligent memories and processing in memory system development experience Data parallel and associative computing Scalable I/O and mass storage in support of massive parallelism Case studies and performance analysis of massively parallel systems and applications Resource management for massively parallel applications Domain specific libraries and application experiences Experience with use of commercial and experimental massively parallel systems System software and tools for massively parallel computing Special Session on Massive Parallelism for Solving Grand Challenge Problems Someone once said "The difference between theory and practice is theoretically negligible but practically worlds apart." Theoretically, the world's super-clusters and supercomputers are capable of enormous peak performance and can be easily programmed in any number of languages. Practically, this is only achievable for certain "pleasantly parallel" (to quote H.J. Siegel) algorithms. This session seeks papers that explore real-world applications executed on massively parallel processing systems. Topics include, but are not restricted to, the following: What applications have been successfully scaled onto MPPs? What unexpected "surprises" (both good and bad) have arisen when scaling onto MPPs? What algorithms are well suited to MPPs that are not so well suited for clusters? What programming environments work best for MPPs? Experimental results showing the human efficiency of one programming language over another, even though "peak performance" (for the processors) is not as high Special Session on Massive Parallelism Using FPGAs for Architecture Research Although we usually think of massive parallelism in terms of larger machines, today's FPGAs contain tens of thousands of logic elements, distributed embedded memory, and flexible interconnect, and are essentially massively parallel processors. What have we learned from MPP systems in a rack that can be applied to MPP systems on a chip? This session is not restricted to FPGAs, but to facilitate comparison, we suggest that results be in terms of FPGA gates, extrapolated to at least 1024 "processors". Topics include, but are not restricted to: What are the issues for Massively Parallel Systems on a Chip? Special purpose processing elements for particular applications that emphasize speed, size, power, simplicity, etc. Single chip (or single card) MPPs as co-processors for workstations Architectural frameworks that combine fixed and customizable components Mapping of older MPPs that used to consume racks of space into a single or multiple FPGAs I/O architectures and methods of interfacing with MPP FPGA's -------------------------------------------------------------------------------- Important Dates: Submissions Due: 9am EST 8 December 2003 Notification of Acceptance: 5 January 2004 Final version Due: 26 January 2004 (TENTATIVE DATE) Submission Guidelines: Authors should submit an electronic version of their paper for review through the online submission form on the WMPP web site by 9am Eastern Standard Time on 8 December 2003. Submissions should be a complete manuscript in Adobe PDF or PostScript format (PDF preferred), formatted single-spaced in a 12 point font, with no more than 12 pages. Submissions must include the submission title; authors' full names, addresses, phone numbers, and FAX numbers; as well as the authors' email addresses. All manuscripts received by this date will be reviewed by the program committee; authors will be notified of the paper's acceptance or rejection by email. -------------------------------------------------------------------------------- Workshop Organizers: Organizing Committee: General Co-Chairs: Robert Walker, Kent State University ( walker@cs.kent.edu ) Johnnie Baker, Kent State University ( jbaker@cs.kent.edu ) Program Co-Chairs: Raymond Hoare, University of Pittsburgh ( hoare@ee.pitt.edu ) Philip A. Wilsey, University of Cincinnati ( paw@ececs.uc.edu ) Publicity Committee: Michael Scherger, Kent State University Program Committee: Nael Abu-Ghazaleh, SUNY Binghamton David Andrews, University of Kansas Johnnie Baker, Kent State University Thomas Braunl, The University of Western Australia Ray Hoare, University of Pittsburgh Mahmut Kandemir, Penn State University Peter Kogge, Notre Dame University H. J. Siegel, Colorado State University Theo Ungerer, University of Augsburg Robert Walker, Kent State University Philip A. Wilsey, University of Cincinnati Jie Wu, Florida Atlantic University