VISUALIZATION

The 10th Reconfigurable Architectures Workshop (RAW 2003) will be held at the Nice Acropolis Convention Center, Nice, France, on April 22, 2003. RAW 2003 is associated with the 17th Annual International Parallel & Distributed Processing Symposium (IPDPS 2003) and is sponsored by the IEEE Computers Society's Technical Committee on Parallel Processing. RAW 2003 is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing. Main Focus of the Workshop: Run-Time & Dynamic Reconfiguration: Architectures, Algorithms, Technologies Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse-grain FPFAs) appear to have more room for exploiting run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2003 aims to provide a forum for creative and productive interaction between all these disciplines. Topics of Interest: Authors are invited to submit manuscripts of original unpublished research in all areas of dynamic and run-time reconfiguration (foundations, algorithms, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and applications). The topics of interest include, but are not limited to: Models & Architectures, Algorithms & Applications, Technologies & Tools: * Theoretical Models * Algorithmic Techniques (RMesh, etc.) * Configurable Systems-on-Chip * Mapping Parallel Algorithms * RTR Models and Systems * Energy Efficiency Issues * RTR Hardware Architectures * Distributed Systems & Networks * Devices and Circuits * Optical Interconnect Models * Fault Tolerance Issues * Reconfiguration Techniques * Wireless and Mobile Systems * Simulation and Prototyping * High Level Design Methods * Automotive Applications, etc * Bounds & Complexity * System support Submission Guidelines: Authors should submit an electronic version of their work for review by October 20, 2002 to Juergen Becker (Universitaet Karlsruhe, becker@itiv.uni-karlsruhe.de) AND register their paper through our web interface at http://www.ece.lsu.edu/vaidy/raw03/ All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript (not to exceed 8 pages of single spaced text, including figures and tables) or, in special cases, may be a summary of relevant work. Submissions should be in pdf-format (preferred), or alternatively in Postscript (level 2) format. Authors should make sure that the submission can be viewed using ghostscript and will print on standard letter size paper (8.5" x 11"). The IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by the IEEE CS Press as a CD-ROM disk. Important Dates: * Manuscript due October 20, 2002 * Notification of acceptance/rejection December 5, 2002 * Final version due January 24, 2003 Organization : Workshop Chair: Serge Vernalde, IMEC, Belgium vernalde@imec.be Steering Chair: Viktor K. Prasanna, University of Southern California, USA prasanna@ganges.usc.edu Program Chair: Juergen Becker, Universitaet Karlsruhe (TH), Germany becker@itiv.uni-karlsruhe.de Publicity Chair: Ramachandran Vaidyanathan, Louisiana State University, USA vaidy@ece.lsu.edu Program Committee: * Jeffrey Arnold, Adaptive Silicon, Inc., USA * Juergen Becker, Universitaet Karlsruhe (TH), Germany * Don Bouldin, University of Tennessee, USA * Gordon Brebner, University of Edinburgh, UK * Klaus Buchenrieder, Infineon Technologies, Germany * Thomas Buechner, IBM, Germany * Oliver Diessel, University of New South Wales, Australia * Carl Ebeling, University of Washington, USA * Hossam ElGindy, University of New South Wales, Australia * Manfred Glesner, Darmstadt University of Technology, Germany * Steve Guccione, Quicksilver Technology, USA * Herbert Gruenbacher, Carinthia Tech. Institute, Austria * Reiner Hartenstein, University of Kaiserslautern, Germany * Brad Hutchings, Brigham Young University, USA * Mark Jones, Virginia Tech, USA * Peter Jung, Gerhard Mercator University, Duisburg, Germany * Mohammed A. S. Khalid, Cadence Design Systems, USA * Hyoung-Joong Kim, Kangwon National University, Korea * Fabrice Kordon, Université Pierre & Marie Curie, Paris, France * Rainer Kress, Infineon Technologies, Germany * Markus Kuehl, Forschungszentrum Informatik (FZI), Karlsruhe, Germany * Rudy Lauwereins, IMEC, Leuven, Belgium * Philip Leong, Chinese University of Hong Kong, China * Marnane Liam, University College, Ireland * Rong Lin, State University of New York, Geneseo, USA * Wayne Luk, Imperial College, UK * Juergen Luka, DaimlerChrysler AG, Germany * Patrick Lysaght, Xilinx, USA * Malgorzata Marek-Sadowska, University of California, Santa Barbara, USA * John McHenry, National Security Agency, USA * Alessandro Mei, University Rome "La Sapienza", Italy * Martin Middendorf, Katholische Universität Eichstätt, Germany * George Milne, University of Western Australia, Australia * Toshiaki Miyazaki, NTT Network Innovation Labs., Japan * Amar Mukherjee, University of Central Florida, USA * Dietmar Mueller, Technische Universitaet Chemnitz, Germany * Koji Nakano, Japan Advanced Inst. of Science & Tech., Japan * Bernard Pottier, Université de Bretagne Occidentale, France * Michel Renovell, LIRMM, France * Peter Roth, IBM, Germany * Sakir Sezer, Queen's University, N. Ireland, U.K. * Hartmut Schmeck, Universität Karlsruhe (TH), Germany * Juergen Teich, University of Paderborn, Germany * Lionel Torres, LIRMM, Montpellier, France * Jerry L. Trahan, Louisiana State University, USA * Ramachandran Vaidyanathan, Louisiana State University, USA * Serge Vernalde, IMEC, Belgium * Martin Vorbach, PACT Informationstechnologie, Germany * Norbert Wehn, University of Kaiserslautern, Germany * Peixin Zhong, Lucent Technologies, USA