VISUALIZATION

The Third Workshop on Massively Parallel Processing builds on the success of the First and Second Workshops, held as part of IPDPS'01 and IPDPS'02. The first and Second workshops featured invited keynote talks by Peter Kogge of Notre Dame, and David Bader of the University of New Mexico, respectively. Each workshop had around 10 papers, and following the usual practice at IPDPS, all papers were published with the paper abstracts in a hardcopy volume and the complete paper in an accompanying CD-ROM. Keynote Speaker: The Third workshop will feature an invited keynote talk by Thomas Sterling (JPL and Cal Tech) that will reflect recent new initiatives by Caltech, Cray, and other institutions under the DARPA High Productivity Computing Systems Program. Further details will be announced later; check the WMPP'03 web site. General Sessions: We are now soliciting papers for the general sessions in the Third workshop. Manuscripts containing original unpublished research are solicited in all areas of massively parallel processing. Topics of interest include, but are not limited to, the following: * Algorithms and models for massively parallel computation * SIMD and MIMD massively parallel systems case studies * Teraflop and petaflop system development and application experience * Intelligent Memories and Processing in Memory system development experience * Data parallel & associative computing * Scalable I/O and mass storage in support of massive parallelism * Case studies and performance analysis of massively parallel systems and applications * Resource management for massively parallel applications * Domain specific libraries and application experiences * Experience with use of commercial and experimental massively parallel systems * System software and tools for massively parallel computing *** Special Session on MPP Using FPGA Metrics for Architecture Research *** Massively parallel processing can be seen in today's FPGA's as they contain over 50,000 logic elements, distributed embedded memory and many layers of flexible interconnect. The Logic Elements/Blocks in a single chip can each implement simple Boolean functions and can be combined to construct more complex building blocks such as counters, signal processing filters and microprocessors. However, the state of the art for System-on-a-Chip (SoC) devices is to contain a single processor like an ARM or PowerPC processor, a bus and peripherals all within a single chip. The complexity of creating these special purpose devices kept designers from utilizing more complex non von Neumann architectures. There are numerous architectures between 50,000 Boolean functions and a single complex microprocessor. What have we learned from MPP systems in a rack that we can apply to MPP systems on a chip or MPP systems on a board? The focus of this session is not restricted to FPGA's but in order to compare different architectures quantifiably, we highly suggest that results be in terms of FPGA gates. We also highly suggest that all results be at least extrapolated to 1024 "processor" even if the design or architecture does not fit within a single FPGA (for now.) The following is a partial list of open issues and topics for single chip MPPs: * What are the issues for Massively Parallel Systems on a Chip? * Quantifiable comparison between SIMD, VLIW, MIMD, Systolic Arrays, etc. * Special purpose processing elements for particular applications that emphasize speed, size, power, simplicity, etc. * Application analysis for parallelisms, memory usage, and/or communication, etc. * Metrics for building MPPs to fit within area, memory and/or power constraints, etc. * Open source benchmarks for MPP * Single chip (or single card) MPPs as co-processors for workstations * Architectural frameworks that combine fixed and customizable components * Design and/or programming methodologies * Case studies of non-MPP devices/applications that could be extended to MPP * Asynchronous verses (or combined with) synchronous architectures * Hierarchical architectures * Architecture and interconnection of tens, hundreds or thousands of FPGA's (or ASIC's) * Mapping of older MPPs that used to consume racks of space into a single or multiple FPGAs * I /O architectures and methods of interfacing with MPP FPGA's * Future directions. What are the critical issues? Submission Guidelines: Authors should submit an electronic version of their work for review to Raymond Hoare at hoare@pitt.edu by midnight Eastern Standard Time on November 1, 2002. Submissions should be a complete manuscript in Adobe PDF or PostScript format (PDF preferred), formatted single-spaced in a 12 point font, with no more than 12 pages. The body of the email submission should clearly give the submission title; authors' full names, addresses, phone numbers, and FAX numbers; as well as the authors' email addresses. All manuscripts received by the date above will be reviewed by members of the program committee, and authors will be notified by email whether or not their paper was accepted. Important Dates: Submissions Due: 1 November 2002 Notification of Acceptance: 15 December 2002 Final version Due: approximately 15 January 2003 Workshop Organizers: Organizing Committee: General Co-Chairs: Johnnie Baker, Kent State University ( jbaker@cs.kent.edu ) Robert Walker, Kent State University ( walker@cs.kent.edu ) Program Co-Chairs: Philip A. Wilsey, University of Cincinnati ( paw@ececs.uc.edu ) Raymond Hoare, University of Pittsburgh ( hoare@ee.pitt.edu ) Program Committee: Nael Abu-Ghazaleh, SUNY Binghamton Johnnie Baker, Kent State University Ray Hoare, University of Pittsburgh Mahmut Kandemir, Penn State University Peter Kogge, Notre Dame University H. J. Siegel, Colorado State University Theo Ungerer, University of Karlsruhe Robert Walker, Kent State University Philip A. Wilsey, University of Cincinnati Publicity Committee: Nael Abu-Ghazaleh, SUNY Binghamton Maher Atwah, Hiram College Ray Hoare, University of Pittsburgh