CSP announced its TeraXP Embedded Servers, featuring OpenVPX payloads with Intel Xeon processors, NVIDIA GPU’s, 10/40GbE and FDR InfiniBand. The TeraXP addresses critical computing requirements in a compact, rugged grade, air-cooled or liquid/conduction-cooled chassis for deployments where reduced size, weight and power (SWaP) are imperative.

The basic building block in the TeraXP family of products is the SMP Server, a two slot configuration comprised of a 6U compute blade and a 6U co-processor blade. Each compute blade implements a Symmetric Multiprocessing (SMP) architecture with the Intel QuickPath Interconnect (QPI) between two Intel Xeon processors and 32 PCIe Gen2 lanes for co-processor support, direct I/O and high performance fabric options. The 6U co-processor blade includes options for a GPU MXM module, an XMC/PMC mezzanine and a Host Channel Adapter (HCA) supporting 10/40GbE, InfiniBand (FDR/QDR/DDR) and the “3000 SERIES Converged Fabric”.

The TeraXP OpenVPX backplane implements three separate data communication planes to maximize performance, flexibility and interoperability. A Data Plane Mesh (8X PCIe Gen2) on P1 delivers ultra low latency for server to server communication, an Expansion Plane (16X PCIe Gen2) on P2 supports GPU co-processors, and the new VITA 66.1 Standard (Optical Interconnect for VPX) on P6 enables scalable fabric’s on the backplane, drastically improving performance and weight over previous copper solutions.

The TeraXP Open Architecture software is based upon non proprietary industry standard components to promote productivity and code reuse at the application layer. This includes the tools, libraries, and middleware needed to support and manage the SMP Servers. The compute blade general purpose processor is supported by Linux with Virtualization, a GNU Toolset, signal processing libraries, OpenMPI and OpenFabrics Enterprise Distribution (OFED) Middleware, and an Intel C++ Compiler Suite. CUDA, OpenCL and OpenACC toolkits are available for the Graphic Processing Units.

“The Open Architecture software stack and the VITA 66.1 standard deliver uncompromising performance today and a clear path for future growth. TeraXP upgrades will support faster Ethernet/InfiniBand fabrics, new Xeon processors, new GPU’s, and new many-core technologies” says Bernard Pelon, CSPI Director of Product Research.

Building on more than 15 years of experience in deployment of High Performance Embedded Computing (HPEC) systems, CSPI’s TeraXP, configured with a few or many servers, delivers a new level of performance and interoperability. These systems address a broad spectrum of sonar, radar, SIGINT, ISR, and imaging applications.

Rugged grade, air-cooled TeraXP 300 systems featuring three SMP Servers with 10/40GbE, FDR InfiniBand and the “3000 SERIES Converged Fabric” support will be available for delivery Q3 2012.