Alliance Semiconductor Corporation, a leading worldwide provider of analog and mixed signal products, high-performance memory products and systems solutions for the communications, computing, embedded, industrial and consumer markets, today announced the availability of its high-performance AS90L10208 HyperTransport™-to-PCI/PCI-X Bridge. The AS90L10208 is designed and optimized for bandwidth- and performance-intensive embedded applications in communications, networking, servers and storage systems. The AS90L10208 is completely interoperable with the HyperTransport (HT) interface on the new generation of leading embedded and compute microprocessors from AMD, Broadcom, PMC-Sierra and Transmeta. The AS90L10208 allows system architects to leverage the performance of these leading microprocessors while still maintaining compatibility with legacy systems. The AS90L10208 bridges the HT interface from these microprocessors to a standard 64-bit PCI/PCI-X bus, enabling them to tap into the vast infrastructure of peripherals and system components based on PCI and PCI-X such as network interface cards (NICs), RAID controllers, host bus adaptors (HBAs) and others. “The AS90L10208 provides system architects with an unlimited set of design options that require the high performance, high bandwidth and high efficiency of the HT bus with the capability to tap into the vast infrastructure of peripherals and system components based on PCI and PCI-X,” said Robert Napaa, vice president of marketing and business development for Alliance’s System Solutions business unit and vice president of the HyperTransport Technology Consortium. The AS90L10208 has two 8-bit HT ports that operate at frequencies up to 800 MHz DDR in both transmit and receive directions and sustains a total aggregate bandwidth up to 25.6 Gbps per HT port. The single 64-bit PCI/PCI-X 1.0b bus operates at frequencies of 25, 33, 50, 66, 100 and 133MHz. This 64-bit PCI/PCI-X bus can be configured to operate as two totally independent 32-bit PCI/PCI-X buses, enabling system design engineers to accommodate 32-bit PCI peripherals and provide further fan-out for down-stream devices. The AS90L10208 can simultaneously work as an HT tunnel device, transferring the data between the two HT ports, or as a bridge device transferring the data between either of the HT ports and the PCI/PCI-X bus. The AS90L10208 can be configured to support dual-hosted chains where a host CPU can be connected to each HT port, enabling them to directly exchange data and to share common system resources across the PCI/PCI-X bus, thus reducing the latency of the data transfer and increasing the system performance. It also maintains full software backward compatibility with Alliance’s first HT-to-PCI bridge, the SP1011, thus reducing development cycle time and leveraging existing software built around the SP1011. Up to 31 AS90L10208 devices can be daisy-chained to build higher capacity systems with multiple PCI/PCI-X buses and HT-based peripherals. A fairness algorithm allocates bandwidth among the devices, thereby eliminating any bandwidth starvation of bridges at the end of the chain. The AS90L10208 is currently sampling and production will begin in 3Q 2004.