WANic 6354 features latest Cavium OCTEON II processor for outstanding performance

GE Intelligent Platforms has announced the WANic 6354 intelligent high performance packet processor designed for demanding high volume IP network applications. Based on the latest multi-core Cavium OCTEON II CN6335-AAP application accelerator processor, its combination of advanced technologies allows for higher speed networks and for the inclusion of advanced security functionality in those networks. With its comprehensive development package designed to minimize time-to-revenue, the WANic 6354 delivers a sustainable competitive advantage to customers.

Evaluation boards will be available in September.

The range of network applications in which the WANic 6354 IP packet processor can be deployed is extremely broad, and includes session border control, secure access, network address translation (NAT), traffic management, firewall, deep packet inspection (DPI) and lawful intercept, secure IP communications, encryption, packet filters, and network monitoring/testing.

"The rapid growth in search engines, cloud computing, Internet-based retailing, Web 2.0, mobile devices, online gaming and so on are driving network traffic at an unprecedented rate," said Rubin Dhillon, Global Director of Communications Product Management at GE Intelligent Platforms. "Huge server farms are becoming the norm. At the same time, concerns about the security and integrity of online communication are uppermost in many customers' minds, as is the need to manage available bandwidth to deliver optimum customer service. The WANic 6354 packet processor is designed to play a central role in these networks, providing a highly cost-effective solution that offloads network processing and enables maximum network throughput."

"Beyond this," continued Dhillon, "the new generation of OCTEON processors delivers a high level of power efficiency with new technology, so that products like the WANic 6354 can make an important contribution to energy savings through lower power consumption."

The new OCTEON II processor delivers up to four times the performance of its predecessor, and is designed to offer more functionality, faster speeds and handle higher traffic flows using the same or less power than its predecessors, enabling the WANic 6354 packet processor to give customers greater performance per watt and greater performance per dollar. It allows applications to efficiently support greater network traffic by offloading traffic processing, and enables customers to enhance their products with network security, encryption and compression support. The alternative would see customers needing to add more general processor computing in the form of server blades, appliances or rack-mount servers. Offloading the traffic processing to the WANic 6354 therefore provides a cost savings to many applications.

Support for IEEE 1588 and hardware timestamping are provided by the WANic 6354 for Ethernet synchronization and packet ordering. This is of particular significance for networks in which voice and video are being transported, and to customers involved in monitoring and evaluating Ethernet traffic as it facilitates reporting flow/timing details for the network being monitored.

The WANic 6354 supports high-speed communications via a 4-lane PCI Express Generation 2 bus interface to the host. Four front panel line interface ports with SFP connectors support IEEE 10/100/1000BaseT Gigabit Ethernet as well as short- and long-reach optical connectivity.

The 4 Gbits/second line-speed packet processing performance for Layers 2-7 of the WANic 6354 is made possible via its use of a number of advanced technologies. These include its MIPS64 Gen 2 processing cores, the implementation of high performance I/O bridging and queuing, its high speed internal connectivity, and its advanced memory technologies: the OCTEON II processor's 2 MBytes of shared L2 cache memory and up to 4 GBytes of high-speed DDR3 packet memory, implemented using dual VLP Mini-RDIMM modules, makes a significant contribution. 512 MBytes of DDR3 SDRAM is implemented for regular expression pattern matching engine memory (HFA/DFA). 32 MBytes of SDRAM is available for use as Persistent Memory in storing processor state information, and up to 16 GBytes of eUSB Flash Disk for bulk memory storage is optionally available.