Mirabilis Design today announced that VisualSim was used by a joint venture project involving TOPS Systems of Japan, to model, simulate and analyze the performance of a Real-Time Ray Tracing system with distributed software and a heterogeneous Multi-Core processor. The architecture development and software partitioning were conducted by developing performance and power models using the standard libraries in the VisualSim graphical environment.  This model was used to optimize the processor architecture, application algorithms and data distribution to achieve 800 trillion floating point operations per second (TeraFLOPS).

“Perfect planning and validation of dynamic performance is absolutely essential to eliminate the considerable architectural and algorithmic risks in developing a system running at supercomputer performance.  Performance of very data dependent processing such as Real-Time Ray Tracing can not be estimated without simulation”, said Dr. Yukoh Matsumoto, Founder and CEO of TOPS Systems.  “We completed the entire modeling effort in VisualSim in three months and achieved an 80% cost reduction for modeling compared with SystemC.  Without VisualSim, the modeling would have required over 1.5 years of development effort.”

Architects at TOPS Systems constructed a model of highly energy-efficient distributed processing system using VisualSim.  The model of the core was built with the partitioned part of application software code. Components in the hardware platform had varying levels of details and accuracy, depending on the analysis to be performed.  This modeling was used to analyze processing loads between cores and to see the bottle necks of the memory hierarchy. The design constraints of the system were the real-time performance, power consumption, and hardware resources implemented on 17mm square of silicon.　　　  

The hierarchical memories and busses model was constructed at cycle-accuracy using pre-built modeling libraries available in VisualSim.  The computational model of each core was constructed based of each application code partitioned for Kahn Process Network based processing model with assertion for counting computation cycles and generating accurate bus transactions for memory accesses. The model combined over a four hundred thousand (400,000) lines of algorithmic C-code with a cluster of heterogeneous Multi-Core processor to create the operating environment for Ray Tracing.  The system consists of 9 processor chips and an additional general purpose processor. Each processor chip consists of 8 clusters of heterogeneous Multi-Core processor, and a general purpose processor. Each cluster consists of 8 heterogeneous cores plus one memory management processor core. In total, 73 heterogeneous cores with hierarchical on-chip memories and interconnects running at 750 MHz per chip were included in the VisualSim model.  The chip is targeted to be fabricated using 45nm manufacturing technology, by integrating 130 million gates and 24Mbit of memory into a 17mm square footprint. VisualSim was able to simulate the Multi-Core processor to achieve performance corresponding to 800 Teraflops which is required for Real-Time Ray Tracing at high-definition (HD) resolution at 1920 x 1080 pixels.  The integration of the software onto the model enabled the model to dynamically compute the processing for complex software and component structures.