CAMPBELL, CA -- Silicon Genesis Corporation (SiGen), a developer of innovative Silicon-On-Insulator (SOI) wafer technologies, has commenced production of a new generation of "ultra-thin" SOI wafers with device layer thicknesses in the range of 15 to 50 nanometers used for fully-depleted substrate CMOS transistor devices. Due to SiGen's unique non-contact smoothing process, the surface roughness of these ultra-thin SOI wafers remains less than 1 Angstrom (0.1 nm) for all silicon layer thicknesses. SiGen's proprietary non-contact epi-smoothing technology eliminates the well-known trade-off between roughness and uniformity faced by wafer manufacturers that utilize contact polishing methods. Ultra-thin SOI layers can be fabricated by the SiGen process on buried oxide (BOX) layers that can be customized over a thickness range from tens of nanometers to a micron or more. This range of available BOX thicknesses for SiGen ultra-thin SOI materials provides the needed design flexibility to optimize transistor designs in this highly-scaled regime. Ultra-thin SOI materials enable the continued performance improvement of electronic devices that has been strongly emphasized in a number of recent product technology announcements and the newly issued International Technology Roadmap for Semiconductors (ITRS). These materials will allow new terahertz bandwidth transistor designs with lower power consumption. The SiGen SOI fabrication process provides for a direct transition to volume production of ultra-thin SOI because the same process tools and many of the same processes are used in the production of its already established thin and thick SOI products, with device layers in the range of 100 to 200 nanometers and several microns, respectively. Ultra-thin SOI wafers have been shipped to leading integrated circuit manufacturers and are available in combination with customized Ge-rich layers for high-mobility CMOS and optical applications. SiGen has also confirmed full process scalability of its technology by successfully transferring ultra-thin layers to 300mm wafers. Dr. Michael Current, SiGen director of Technology Marketing and member of the ITRS Starting Materials Technical Working Group, said, "A key advantage of our approach to ultra-thin SOI layers is the non-contact nature of the SiGen process for establishing the final layer thickness and surface finish. This allows us to manufacture ultra-thin SOI wafers without compromising such critical characteristics as surface roughness and layer thickness uniformity control. The reliable fabrication of semiconductor on oxide layers of less than 20 nanometers may also enable the formation of device quality, high-Ge content layers and strained-Si structures for high-mobility CMOS channels. We expect that the development of these techniques will lead to a new generation of high mobility 'turbo-charged' electronic materials beyond the present types of Si-only wafers." For additional information visit www.sigen.com