Call For Papers - Workshop on Communication Architecture for Clusters (CAC '03)To be held in Conjunction with Int'l Parallel and Distributed Processing Symposium (IPDPS '03) Nice Acropolis Convention Center, Nice, France April 22-26, 2003 The availability of commodity PCs/workstations and high-speed networks (Local Area Networks and System Area Networks) at low prices enabled the development of low-cost clusters. These clusters are being targeted for support of traditional high-end computing applications as well as emerging applications, especially those requiring high-performance servers. Designing high-performance and scalable clusters for these emerging applications requires design and development of high-performance communication and I/O subsystems, low-overhead programming environment support and support for Quality of Service (QoS). New user-level communication protocol standards such as Virtual Interface Architecture (VIA) and InfiniBand Architecture (IBA) are providing exciting ways to design high-performance communication and I/O architectures for clusters. A large number of research groups from academia, industry, and research labs are currently engaged in the above research directions. The goal of this workshop is to bring together researchers and practitioners working in the areas of communication, I/O, and architecture to discuss state-of-the-art solutions as well as future trends for designing scalable, high-performance, and cost-effective communication and I/O architectures for clusters. The first two workshops in this series (CAC '01 and CAC '02) were held in conjunction with IPDPS conferences, and they were very successful. The CAC '03 workshop plans to continue this tradition. TOPICS OF INTEREST: Topics of interest for the workshop include but are not limited to: 1. Router/switch, network, and network-interface architecture for supporting efficient point-to-point communication, collective communication, and I/O at intra-cluster and inter-cluster levels. 2. Design, development, and implementation of communication protocols (GM, VIA, TCP/IP, etc) on different networking and interconnect technologies (such as Myrinet, Gigabit Ethernet, InfiniBand, Quadrics, TCP Offload Engine, etc.). 3. High-performance implementation of different programming layers (Message Passing Interface (MPI), Distributed Shared Memory such as TreadMarks, Get/Put, Global Arrays, sockets, etc.) and File Systems (such as PVFS and DAFS). 4. Communication and architectural issues related to switch organization, flow control, congestion control, routing and deadlock-handling, load balancing, reliability, and QoS support. 5. Strategies, algorithms, and protocols for management of communication resources, including topology discovery, hot update/replacement of components, dynamic reconfigurations, etc. 6. Performance evaluation and tools for different application areas, including interprocessor communication and I/O, etc. Results of both theoretical and practical significance will be considered. PROCEEDINGS: The proceedings of this workshop will be published together with the proceedings of other IPDPS '03 workshops by the IEEE Computer Society Press. PAPER SUBMISSIONS: We are planning a purely electronic submission and review process. Authors are requested to submit papers (in PDF format) not exceeding 10 single-spaced pages, including abstract, five key words, contact address, figures, and references. E-mail your manuscripts to: cac@cis.ohio-state.edu. Note: the PDF file must be viewable using the "acroread'' tool. It is also important, when creating your PDF file, to use a page size of 8.5x11 inches (LETTER sized output not A4), since an A4 sized page may be truncated on a LETTER sized printer. SCHEDULE: Paper submission: November 4, 2002 Notification of acceptance: December 16, 2002 Camera-ready due: January 24, 2003 WORKSHOP CO-CHAIRS: Dhabaleswar K. Panda (Ohio State), Jose Duato (Univ. of Valencia, Spain), and Craig Stunkel (IBM TJ Watson Research Center) PROGRAM COMMITTEE: Bulent Abali (IBM TJ Watson) Mohammad Banikazemi (IBM TJ Watson) Angelos Bilas (Univ. of Toronto, Canada) Alan Benner (IBM) Ron Brightwell (Sandia National Lab) Toni Cortes (UPC, Spain) Wu-Chun Feng (Los Alamos National Lab) Jose Manuel Garcia (Univ. of Murcia, Spain) Mitchell Gusat (IBM, Zurich) Mark Heinrich (Cornell Univ.) Manolis G.H. Katevenis (FORTH and Univ. of Crete, Greece) Nectarios G. Koziris (National Technical Univ. of Athens, Greece) Mario Lauria (Ohio State) Olav Lysne (Univ. of Oslo, Norway) Arthur (Barney) Mccabe (Univ. of New Mexico) Pankaj Mehra (HP) Shubu Mukherjee (Intel) Jarek Nieplocha (Pacific Northwest National Lab) Scott Pakin (Los Alamos National Lab) Fabrizio Petrini (Los Alamos National Lab) Greg Pfister (IBM) Timothy Pinkston (Univ. of Southern California) Antonio Robles (UPV, Spain) Tom Rokicki (Instantis) Reza Rooholamini (Dell) Hemal Shah (Intel) Anthony Skjellum (Mississippi State) Pete Wyckoff (Ohio Supercomputer Center) Xiaodong Zhang (NSF) PUBLICITY COORDINATORS: Darius Buntinas (Ohio State University) Nectarios G. Koziris (National Technical Univ. of Athens, Greece) ADDITIONAL INFORMATION: On the World Wide Web, see http://www.cis.ohio-state.edu/~cac for the latest information about this workshop. Alternatively, you can send e-mail to cac@cis.ohio-state.edu.