NetLogic Microsystems has announced the industry's first fully deterministic intelligent networking solution capable of concurrently processing advanced Layers 2 - 7 functions at 40Gbps wire-speed. By using market-leading, best-in-class multi-core processing and knowledge-based processing technologies from NetLogic Microsystems, the new innovative NLX321103A solution enables the simultaneous and deterministic processing of complex networking functions such as deep packet content inspection, application-aware switching and routing, intrusion prevention (IPS), anti-virus/malware, network service management, packet ordering, parsing, IPv6/IPv4 forwarding, classification, IPSec/SSL encryption, ACL security, compression/decompression and quality-of-service (QoS) at 40Gbps wire-speed.

The exponential growth of converged voice, video and data traffic over IP-based networks, coupled with the rapid adoption of services and applications over mobile devices, is driving the need for networking equipment to concurrently support all Layers 2 through 7 functions and to be able to process network traffic at wire speeds and with full determinism. Because available competitive solutions provide non-deterministic, high latency and best-effort packet processing, networking original equipment manufacturers (OEMs) have been forced to compromise network integrity by separating Layers 2 - 4 and Layers 4 - 7 processing on different cards and then selectively performing certain functions only on a fraction of the traffic. NetLogic Microsystems' 40Gbps NLX321103A solution enables next-generation switches, routers, access aggregation, metro Ethernet, service gateways, security appliances and storage appliances to perform uncompromised L2 - L7 packet processing on every packet of traffic with minimal network latency under a wide variety of Internet traffic scenarios, which in turn ensures predictable network behaviors and eliminates network bottlenecks.

NetLogic Microsystems' 40Gbps wire-speed L2 - L7 solution incorporates 32 NXCPUsss from its best-in-class XLP multi-core, multi-threaded processor family, along with 128 knowledge-based processing engines, 196 Intelligent Fabric for Automata (IFA) engines from its market-leading NETL7       processor family and over 40 fully-autonomous programmable processing engines -- all tightly coupled and working in concert to deliver deterministic wire-speed performance.

"Our new L2 - L7 NLX321103A solution is a game changer for the industry as it provides customers with the unprecedented ability to develop a new class of highly differentiated networking systems that deliver deterministic line-rate throughput while supporting L2 - L7 functionality," said Chris O'Reilly, vice president of marketing at NetLogic Microsystems. "This further demonstrates our unique capabilities to drive innovations across multiple product lines and to deliver new levels of performance that are unparalleled in the industry."

"NetLogic Microsystems is uniquely positioned to deliver this integrated L2 - L7 system solution that leverages the company's multiple generations of its multi-core processors, knowledge-based processors and content processors," said Bob Wheeler, senior analyst at The Linley Group. "The explosive growth of video and mobile-data traffic has made the determinism and line-rate throughput of functions such as IPv6 classification and deep-packet inspection extremely critical to the overall performance for next-generation networks."

"As a leading provider of complete ATCA platform solutions for the Long Term Evolution (LTE), Femtocell and Deep Packet Inspection (DPI) markets, we have been very impressed with NetLogic Microsystems' technology leadership across all its product lines," said Mike Coward, CTO at Continuous Computing. "We are excited to be offering our latest generation ATCA products using NetLogic Microsystems' multi-core, multi-threaded processors and knowledge-based processors."

Central to the L2 - L7 processing solution is the industry's leading XLP multi-core, multi-threaded processor, which is powered by 32 NXCPUs that operate at up to 2.0 GHz and are based on a highly innovative superscalar engine with out-of-order execution capabilities to deliver unparalleled data plane and control plane performance, as well as the ability to support billions of in-flight messages and packet descriptors. The XLP cores are quad-threaded to effectively minimize bottlenecks and memory latencies that are inherent in network data-plane processing applications. Furthermore, the 32 NXCPUs are equipped with a tri-level cache architecture with over 12.5 Mbytes of fully coherent on-chip cache which delivers 40 Terabits/sec of extremely high-speed on-chip memory bandwidth. The XLP processor also includes over 40 fully-autonomous programmable processing engines that provide independent and complete offload of additional network functions, including IPSec/SSL security encryption/decryption/authentication, packet parsing, packet queuing, packet management, compression/decompression, packet ordering, storage de-duplication, RAID5/RAID6, TCP segmentation and IEEE1588 hardware time stamping. The XLP processor is designed on TSMC's high performance 40nm process, providing for the smallest die size, highest clocking speeds and industry-leading power profile.

To complement the 32 NXCPUs, the XLP832 multi-core, multi-threaded processor interfaces directly over a 50Gb/s high-speed, low-latency serial bus to the NL11k knowledge-based processor, giving the CPUs high-speed access to 128 of NetLogic Microsystems' market-leading knowledge-based processing engines to deliver up to 1.0 billion decisions per second of advanced Layers 2 - 4 flow classification, IPv4/IPv6 forwarding, ACL security and quality-of-service (QoS) policing. The NL11k is also produced in TSMC's 40nm high performance process, again delivering optimum die size, performance and power. The combination of the breakthrough innovations in the XLP multi-core, multi-threaded processor and NL11k knowledge-based processor, along with the high-speed interconnect allows this solution to deliver 15x the Layer 4 performance of existing solutions, thereby enabling an entirely new set of application scenarios for next-generation Internet networks.

To complete the solution, the 32 NXCPUs interface over a second set of high-speed serial busses to provide direct CPU connection to 196 of NetLogic Microsystems' third-generation Intelligent Fabric for Automata (IFA) engines from the NETL7 Layer 7 knowledge-based processor family. These IFA engines are highly optimized to inspect millions of network flows against hundreds of thousands of complex Perl Compatible Regular Expression (PCRE) signatures, and have a unique ability to natively perform stateful cross-packet inspection in hardware. The IFA engines integrate on-chip memory and provide over 500 Terabits per second (Tbps) of ultra-low latency access bandwidth to on-chip signature databases to effectively accelerate complex and iterative content inspection, while eliminating the need to provision for the high-latency and costly off-chip memory that are required by competing solutions. The third-generation IFA engines also provide support for over 76.6 Tbps of state transition bandwidth.

The NLX321103A solution requires no external glue-logic for connection among the processors and is supported by a unified software platform to accelerate customer adoption of this breakthrough capability. The resulting wire-speed Layer 2 - 7 functionality will fundamentally change network architectures by allowing full Layer 7 packet processing without introducing a bottleneck that slows down Internet traffic.

The NLX321103A solution is expected to sample in the third quarter of 2010 and NetLogic Microsystems is now engaging with early adopters of this technology.